Memory-centric computing has been actively researched for AI application. To achieve this, there are growing demands on memories for high density and high endurance. To demonstrate the application, a variety of emerging memory technologies have been proposed; however, they still have difficulties in achieving a density comparable to NAND flash and in improving endurance.CAAC-IGZO, with a wide bandgap and a heavy hole effective mass, can be applied to a field-effect transistor that is characterized by its extremely-low off-leakage current. Use of CAAC-IGZO FET in non-display fields has been reported in recent years, and 3D NAND utilizing CAAC-IGZO FET has been researched. However, the reported memory cell architecture involves through-dielectric charge trapping in MONOS structures, and has low endurance in the same way as conventional Si-based NAND flash.In view of the above, we propose a 3D OS NAND memory, a vertically-stackable 2Tr-1C memory having CAAC-IGZO FETs. Potentially, this memory not only enjoys main features of NAND flash such as high density and non-volatility, but also achieves a DRAM-like endurance. In this study, we evaluated our novel memory architecture with TCAD Sentaurus produced by Synopsys.The cross section, circuit diagram, and 3D overall structure of the memory cell are shown in Fig. 1(a), Fig. 1(b), and Fig. 1(c), respectively. The 3D OS NAND has a memory cell architecture in which a pair of vertically-positioned transistors on the A-A' plane is connected in series to another pair in the Z-axis direction. Taking advantage of extremely-low off-leakage current of CAAC-IGZO FET, the memory cell is composed of only a switching CAAC-IGZO FET and a MIM capacitor. The timing chart of a string of four memory cells connected in the Z-axis direction is shown in Fig. 1(d). Write operation is performed by sequentially lowering the voltage of WG from the bottom with respect to the Z-axis direction, and read operation is performed by lowering the voltage of CG of the memory cell being read. The retention properties of memory cells to which a checker pattern is written are shown in Fig. 1(e). The device simulation indicates a possibility that a memory cell composed of only an CAAC-IGZO FET and a MIM capacitor achieves a retention time of 109 sec or longer. In this paper, we propose a novel memory architecture with CAAC-IGZO FET by discussing the overview of 3D OS NAND and its write and read performance. Fig. 1(a) Cross section of 3D OS NAND memory cell, (b) circuit diagram of 3D OS NAND memory cell, (c) 3D structure of 3D OS NAND, (d) timing chart of 3D OS NAND, and (d) retention properties of 3D OS NAND Figure 1
Read full abstract