Hardware Reuse Research Articles

Infective endarteritis of coronaries following percutaneous coronary intervention (stentocarditis) leading to pseudoaneurysm - a retrospective study of eleven cases.

Coronary endarteritis and stent abscess following percutaneous coronary intervention (PCI) are rare and challenging conditions with no clear treatment guidelines available. This retrospective study aims to present the clinical features, patient and procedural factors, management strategies, and outcomes in 11 consecutive cases referred between 2018 and 2022. We retrospectively analysed 11 cases of coronary endarteritis and stent abscess post-PCI that were referred from various centres. We recorded clinical features, patient demographics, procedural factors, and management approaches, and evaluated treatment outcomes. Among the 11 patients, 7 (63.6%) were male. PCIs had been performed in the right coronary artery (6, 54.5%), left anterior descending artery (3, 27.3%), and circumflex artery (2, 18.2%). The presenting symptoms included fever, pericarditis with effusion, tamponade, and postinterventional angina due to stent occlusion. Fever occurred in 10 (90.9%) patients, and the majority (70%) of patients experienced fever within one week of PCI. Staphylococcus aureus was the predominant organism (54.5%), followed by Pseudomonas aeruginosa. Transthoracic echocardiography revealed abscess cavities in 10 patients. All patients received vancomycin and piperacillin-tazobactam. Surgery was considered in 7 cases with abscesses >2 cm; one patient refused and responded to antibiotics for 4 weeks. Possible risk factors included repeated use of local sites, reuse of hardware, multiple guidewire manipulations, prolonged catheterisation, inadequate sterility, and diabetes. This study provides insights into coronary endarteritis and stent abscess following PCI. The lack of clear treatment guidelines highlights the challenges in managing this condition. Identifying risk factors may aid in preventive strategies. Further research is needed to develop standardised approaches for effective management.

Review of Advanced Methods in Hardware Acceleration for Deep Neural Networks

Abstract: Convolutional neural networks have become very efficient in performing tasks like Object Detection providing human like accuracy. However, their practical implementation needs significant hardware resources and memory bandwidth. In recent past a lot of research is being carried out for achieving higher efficiency in implementing such neural networks in hardware. We talk about FPGAs for hardware implementation due to their flexibility for customisation for such neural network architectures. In this paper we will discuss the metrics for efficient hardware accelerator and general methods available for achieving an efficient design. Further, we will discuss the actual methods used by recent research for implementation of deep neural networks particularly for object detection related applications. These methods range from actual ASIC design like TPUs [1] for on chip acceleration, state of the art open source designs like Gemini to methods like hardware reuse, re-configurable nodes and approximation in computations as a trade-off between speed and accuracy. This paper will be a valuable summary for the researchers starting in the field of hardware accelerators design for neural networks

Multi-cut based architectural obfuscation and handprint biometric signature for securing transient fault detectable IP cores during HLS

This paper presents a novel dual defense security methodology for fault detectable reusable hardware intellectual property (IP) core against reverse engineering and piracy using multi-cut based architectural obfuscation and handprint biometric signature, useful for consumer electronics (CE) systems. The proposed approach, firstly generates a fault detectable design corresponding to target application framework. Subsequently, multiple cut insertion is executed resulting in multi-checkpointing which in turn camouflages the hardware design architecture during high level synthesis (HLS), thereby making it uninterpretable for an adversary. Next, handprint biometric signature of IP vendor is covertly embedded into the fault detectable IP design, which provides robust and seamless detective countermeasure against piracy. The proposed methodology achieves the following: a) strength of obfuscation ∼14 % b) robust detective control against piracy using handprint biometric signature at 0.0 % design cost overhead c) robust security in terms of digital proof against piracy as evident from lesser probability of coincidence and higher tamper tolerance.

A 3.02 pJ/Bit 3T-APS-Based In-Sensor Strong PUF Featuring Near-100% Hardware Reuse Ratio and High Resilience to Machine Learning Attacks

In this brief, we present an energy-efficient in-sensor strong physical unclonable function (PUF) based on the static entropy of 3-transistor active pixel sensor (3T-APS) structure that is widely-adopted in the CMOS image sensors (CIS). With ultra-small silicon area overhead of 0.25% dedicated to the added bias circuitries for column line and digital comparator for PUF bit generation, traditional 3T-APS-based CIS can be well-reused to construct the proposed strong PUF for authenticating the recorded images or videos. Taking advantage of the inherent high-resolution pixel array of CIS, the proposed strong PUF significantly extends the challenge-response-pair (CRP) space of the previous implementations. In addition, large CRP nonlinearity can be obtained by biasing the selected 3T-APS pixels at the subthreshold region, which further increases the complexity of the above extended CRP space and its resilience to various machine learning (ML) attacks. Moreover, the proposed strong PUF design is validated by the extensive measurement results of the prototype chips fabricated using a standard 65-nm CMOS process. Featuring a low energy consumption of 3.02 pJ/bit and a high area efficiency of 1.64×1033 bit/F2, prediction error of 49.1% 51.84% can be achieved under various ML attacks based on artificial neural network, logistic regression, support vector machine and covariance matrix adaptation evolution strategy, with the number of adopted CRPs for training up to 10 million.

Exploration of optimal crypto-chain signature embedded secure JPEG-CODEC hardware IP during high level synthesis

The design process of the JPEG-CODEC as a reusable hardware intellectual property (IP) core for electronic and multimedia systems involves conflicting design goals such as area and latency, alongside providing hardware security against IP piracy and false claims of IP ownership during high-level synthesis (HLS). The proposed work introduces the following novelties: (a) firefly algorithm (FFA)-driven design space exploration (DSE) for generating optimal design solution of secure JPEG-CODEC hardware IP design during HLS, (b) covert security constraints generation process based on key-driven crypto-chain driven hardware security methodology during performing area-latency tradeoff, (c) embedding process that integrates covert security constraints into the design of the JPEG-CODEC. The proposed approach enables the detection of IP piracy and false IP ownership claim. The proposed methodology obtains stronger tamper tolerance ability of > ∼10,116 times and enhanced digital evidence (probability of coincidence) of > ∼102 times than similar recent techniques at lesser design cost. Moreover, the proposed approach attains stronger entropy value of > ∼1078 times than similar recent techniques.

A Low-Power ECG Processor ASIC Based on an Artificial Neural Network for Arrhythmia Detection

The early detection of arrhythmia can effectively reduce the risk of serious heart diseases and save time for treatment. Many healthcare devices have been widely used for electrocardiogram (ECG) monitoring. However, most of them can only complete simple two-classes detection and have unacceptable hardware overhead and energy consumption. For achieving accurate and low-power arrhythmia detection, a novel ECG processor application specific integrated circuit (ASIC) is proposed in this paper, which can perform the prediction of five types of cardiac arrhythmias and heart rate monitoring. To realize hardware-efficient R-peak detection, an ECG pre-processing engine based on a first derivative and moving average comparison method is proposed. Efficient arrhythmia detection is realized by the proposed low-power classification engine, which is based on a carefully designed lightweight artificial neural network (ANN) with good prediction accuracy. The hardware reuse strategy is used to implement the hardware logic of ANN, where computations are executed by only one processing unit (PU), which is controlled by a flexible finite state machine (FSM). Also, the weights of ANN are configurable to facilitate model updates. We validate the functionality of the design using real-world ECG data. The proposed ECG processor is implemented using 55 nm CMOS technology, occupying an area of 0.33 mm2. This design consumes 12.88 μW at a 100 kHz clock frequency, achieving a classification accuracy of 96.69%. The comparison results with previous work indicate that our design has advantages in detection performance and power consumption, providing a good solution for low-power and low-cost ECG monitoring.

DESIGN FOR X: ENABLING THE REUSE OF SPACE HARDWARE?

AbstractWith a growing number of objects in space, the pressure to be sustainable and more efficient with resources is increasing. Driven by technological advancements, the reuse of space hardware becomes feasible and viable as alternative to spacecraft end-of-life disposal. Reuse of space hardware promises benefits in areas like mitigating space debris risks, cost reductions, and environmental sustainability on Earth and in space. However, challenges related to the space environment, like micro gravity, unknown changes due to radiation, and the energy requirements to perform maneuvers in space must be addressed in order to enable spacecraft reusability. Nonetheless, reuse of space hardware is an important objective related to long-term space exploration with implications on the human expansion into space. This paper investigates the requirements for reusability of spacecraft and if circular economy strategies can support implementing reusability for spacecraft. Based on the finding of expert interviews, it argues for design as a key enabler. It introduces design for X, design for circularity, and design for reusability, and explores how reusability of space hardware implies the need to include the space environment in design decisions.

Quadruple phase watermarking during high level synthesis for securing reusable hardware intellectual property cores

Reusable hardware intellectual property (IP) cores play a significant role in the modern system on chip (SoC) designs. However, raging threats of IP piracy and IP ownership infringement sabotage revenue and reputation of genuine IP vendors. This paper presents a novel quadruple phase watermarking for securing hardware IP cores during high level synthesis (HLS). The proposed approach introduces several novelties: graph partitioning, encoding tree, and eightfold mapping to generate a robust watermarking signature. Further, embedding signature during four phases of HLS viz. scheduling, register binding, resource binding and interconnect binding leads to a high-quality watermark. The proposed results indicate multiple times lower Pc and higher tamper tolerance than previous approaches, at negligible design cost overhead. We achieved improvements in Pc and tamper tolerance up to 1018 and 1052 times respectively than related works. Finally, security and design cost tradeoff for various signature strengths is presented.

ERDAC: Efficient and Reliable Remote Direct Access and Control for Embedded Systems

Emerging embedded systems, such as autonomous vehicles, demand highly efficient remote data transfer, whereas existing networking hardware and protocols cause high communication latency and CPU consumption. In this article, we propose embedded RDAC (eRDAC), an efficient and reliable remote direct access and control solution for embedded systems. The proposed remote access controller in eRDAC has a two-layer protocol offload engine that employs the command/response protocol on UDP to ensure the data reliability and security, and a multichannel DMA controller with configurable priority to improve the efficiency. Besides, a reusable hardware Ethernet MAC is implemented to support not only remote access commands but also standard Ethernet communication. We implement eRDAC on FPGA and the corresponding software in the Linux system. Experimental results show that eRDAC can reduce the latency of remote I/O reading/writing by 74.3%/74.9% ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3.76\times /3.98\times $ </tex-math></inline-formula> performance improvement) and reduce the latency of remote memory reading and writing with 1024B by 54.2% compared to the socket-based communication. Meanwhile, eRDAC can cut off the consumption of the remote processor and achieve 0.250mJ/Mb energy consumption with only 25-mW power.

Improved firefly algorithm–extended Kalman filter–least-square support-vector machine voltage sag monitoring and classification method based on edge computing

Aiming at the hardware reusability, multi-service carrying capacity, and computing resource limitations of edge devices, a light-weight voltage sag monitoring and classification method based on improved firefly algorithm optimization, extended Kalman filter, and least-square support-vector machine is proposed. The strategy of linearly decreasing inertia weight is introduced to optimize the state error of the extended Kalman filter algorithm and the measurement noise covariance matrix to achieve accurate monitoring of voltage sags. Extract characteristic quantities such as average value, duration of sag, minimum sag dispersion characteristics, number of sag phases, and flow direction of disturbance energy. As a model training data set, the least-square support-vector machine method optimized based on the improved firefly algorithm is used to create a multi-level classification model of voltage sag source to realize the classification of voltage sag sources. This method fully considers the influence of the limited resources of edge computing equipment on the algorithm, and effectively improves the use of computing resources by improving the optimization algorithm. Simulation and experimental results show that this method is suitable for edge computing equipment to monitor and distinguish voltage sags.

Introducing readiness scales for effective reuse of open source hardware

Open source hardware (OSH) describes physical products that allow for "anyone to study, modify, produce, and distribute them". While OSH principles aim to support design reuse, recent studies have challenged whether this is properly applied in practice. Therefore, this article delivers an assessment scheme that allows to identify the readiness of OSH designs for reuse. Testing the scheme on OSH ventilator designs collected by the Publnv ventilator project showed overall good usefulness of the scheme and emphasised the need of unambiguous assessment scales based on common standards. Less than two thirds of Publnv’s listed projects fulfilled minimum criteria for openness.

Hardware Update through Digital TV Signals

This paper presents a new hardware reconfiguration approach named hardware reconfiguration through digital television (HARD), which can update FPGA hardware modules based on digital TV (DTV) signals. Such a scheme allows several synthesized hardware cores (bitstreams) signaled and broadcast through open DTV signals via data streaming to be identified, acquired, decoded, and then used for system updates. Reconfiguration data are partitioned, encapsulated into private sections, and then sent in a carrousel fashion in order to be recovered by modified receivers. Service information content, specially designed for identifying and describing the characteristics of multiplexed hardware bitstreams, was added to the transmitted signal and provided all necessary information in the traditional DTV style. The receiver framework, in turn, checked whether those characteristics corresponded to its embedded reconfigurable devices and, if a match was found, it reassembled the related bitstreams and reconfigured the respective internal circuits. Experiments performed with an implementation of the proposed methodology confirmed its feasibility and showed that remounting and reconfiguration times were satisfactory and presented no blocking aspect. Finally, HARD can be used in several designs regarding intelligent reconfigurable devices, minimize device costs in the long term, and provide better hardware reuse.

Towards Quantum One-Time Memories from Stateless Hardware

A central tenet of theoretical cryptography is the study of the minimal assumptions required to implement a given cryptographic primitive. One such primitive is the one-time memory (OTM), introduced by Goldwasser, Kalai, and Rothblum [CRYPTO 2008], which is a classical functionality modeled after a non-interactive 1-out-of-2 oblivious transfer, and which is complete for one-time classical and quantum programs. It is known that secure OTMs do not exist in the standard model in both the classical and quantum settings. Here, we propose a scheme for using quantum information, together with the assumption of stateless (i.e., reusable) hardware tokens, to build statistically secure OTMs. Via the semidefinite programming-based quantum games framework of Gutoski and Watrous [STOC 2007], we prove security for a malicious receiver making at most 0.114n adaptive queries to the token (for n the key size), in the quantum universal composability framework, but leave open the question of security against a polynomial amount of queries. Compared to alternative schemes derived from the literature on quantum money, our scheme is technologically simple since it is of the "prepare-and-measure" type. We also give two impossibility results showing certain assumptions in our scheme cannot be relaxed.

Efficient Incorporation of the RNS Datapath in Reverse Converter

The class of moduli sets in the form of {2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</sup> , 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> -1, 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> +1, m <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> } with m <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> ∈ {2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">r</sup> +1, 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">r</sup> -1} has earned significant popularity in the implementation of the Residue Number System (RNS)-based computational systems, mainly thanks to the efficient arithmetic unit and a high degree of parallelism. However, its complicated inter-modulo computation leads to a high overhead associated with the complex reverse converter. This overhead is the main barrier for energy-efficient implementation of RNS-based devices, particularly for edge computing applications. This brief presents a new approach that embeds the reverse converter into the arithmetic unit of the RNS processor for the aforesaid well-known class of moduli sets. The effective hardware reuse in the proposed approach leads to an area and energy-efficient RNS realization for this class of moduli set. The experimental results based on 65 nm CMOS technology indicate the superiority of RNS realization by employing the proposed design methodology. The proposed architecture for a given RNS provides a substantial 17.4% area-saving and 13.32% less power-consumption on average compared to the traditional design approach, with the negligible penalty in delay.

A Multifunctional Unit For Reverse Conversion and Sign Detection Based on The 5-Moduli Set

The high dynamic range residue number system (RNS) five-moduli { 2 2n , 2 n + 1, 2 n − 1, 2 n + 3, 2 n − 3 } has been recently introduced as an arithmetically balanced five-moduli set for computation-intensive applications on wide operands such as asymmetric cryptography algorithms. The previous dedicated design of RNS components for this moduli set is just an unsigned reverse converter. In order to utilize of the moduli set { 2 2n , 2 n + 1, 2 n − 1, 2 n + 3, 2 n − 3 } in applications handling with signed numbers, two important components are needed: Sign Detector and Signed Reverse Converter. However, having both of these components results in high hardware requirements which makes RNS impractical. This paper overcomes to this problem by designing a unified unit which can perform both signed reverse conversion as well as sign detection through the reuse of hardware. To the authors knowledge, this is the first attempt to design sign detector for a moduli set including 2n±3 moduli. In order to achieve a hardware-amenable design, we first improved the performance of the previous unsigned reverse converter for the moduli set { 2 2n , 2 n + 1, 2 n − 1, 2 n + 3, 2 n − 3 }. Then, we extract a sign detection method from the structure of the reverse converter. Finally, we make the unsigned reverse converter to sign converter through the use of the extracted sign signal from the reverse converter. The experimental results shown that the proposed multifunctional unit has relatively the same performance in terms of area, delay and power-consumption than the previous unsigned reverse converter for the set { 2 2n , 2 n + 1, 2 n − 1, 2 n + 3, 2 n − 3 } while it can perform two complex signed operations.

Hardware Sharing for Channel Interleavers in 5G NR Standard

Interleaver module is an important part of modern mobile communication system. It plays an important role in reducing bit error rate and improving transmission efficiency over fading channels. In 5G NR (5th Generation New Radio) standards, LDPC (low-density parity-check) and polar channel codes are employed for data channels and control channels, respectively. If multiple interleavers are implemented separately for them, the cost increases significantly. To address this issue, a hardware multiplexing scheme for channel interleavers based on LDPC and polar codes is proposed in this paper. Firstly, the formulas for the processes of the control channel interleaving and data channel interleaving are derived with respect to 5G NR standard. Then, the hardware implementation structures of the two interleavers are given. Subsequently, hardware reuse is proposed by sharing the similar or identical parts between the two hardware structures. Simulation results verify the correctness of our proposed scheme and demonstrate that it can realize the hardware sharing of the two kinds of channel interleavers to reduce the cost of silicon.

DESIGN OF A LOW LATENCY ROUTER FOR ON-CHIP NETWORKS

A problem with long on-chip wires is the resulting delays, and repeater insertion becomes essential to mitigate this problem. Point-to-point wiring leads to an increase in the area and repeater insertion leads to an increase in power consumption. The complexity of System-on-Chip (SoC) designs continues to increase, and traditional bus-based interconnects will not be sufficient to manage the communication requirements of future billion transistor chips. The properties of our OCN are now reviewed. The OCN provides reliable communication. This is achieved by ensuring that data dropping is not allowed. On-Chip Network’s (OCN’s) provide a scalable alternative to existing on-chip interconnects. The key element of the OCN is the router. We present a prototype design of a 5-input, 5-output, scalable router. The router is constructed from a collection of parameterizable and reusable hardware blocks and is a basic building block of the OCN.

An Efficient VLSI Architecture for FastICA by Using the Algebraic Jacobi Method for EVD

Blind source separation (BSS) is a problem that appears in many research fields. Fast Independent components analysis (FastICA) is one of the techniques to solve the problem. The researchers have verified the effectiveness of the technique through the offline analysis of the public datasets. The development of a real-time portable system involving such a computationally complex analysis requires an efficient hardware implementation of FastICA. A Field programmable gate array (FPGA) and an application-specific integrated circuit (ASIC) are two promising hardware platforms to implement FastICA. This work proposes a new method, called ALgebraic Jacobi Method (ALJM), for performing eigenvalue decomposition (EVD) required for the implementation of FastICA. We use a simplification, a polynomial approximation, and the Newton-Raphson method for calculating the Jacobi rotation. In this way, we ensure hardware reusability between the EVD stage and the weight vector estimation (WVE) stage of FastICA which reduces the computational complexity and the power consumption, without compromising its computation speed. We evaluate the ALJM-based FastICA by performing BSS on the linear mixtures of the deterministic and the random signals and comparing the performance results with the existing methods. After verifying its functionality and numerical stability, we propose a scalable systolic processing array (SPA) for the ALJM-based FastICA and implement it on Spartan-6 FPGA. By comparing the existing implementations of FastICA, in terms of speed, area, and power, we conclude that the ALJM-based FastICA is one of the most efficient methods for prototyping and commercializing a real-time portable system comprising FastICA.

Area and Power-Efficient Variable-Sized DCT Architecture for HEVC Using Muxed-MCM Problem

This paper presents an area and power-efficient variable-size DCT architecture for HEVC application. We develop a reconfigurable and scalable shift-and-add unit (SAU) embedded in our 1D-DCT architecture by leveraging Muxed-MCM problem with the aim of increasing the hardware reusability in the arithmetic units, while reducing the hardware cost. The key idea behind the proposed architecture is the fact that in most of the times (≈90%) the lower point DCTs are performed when the higher point SAUs remain unused. Accordingly, we focus on merging the SAUs of lower point DCTs into the higher point DCTs to compute multiple lower point DCTs in parallel as well as processing any combination of transform sizes. The experimental results show that the proposed folded and fully-parallel 2D-DCT architectures achieve the best hardware cost by 45% and 30% reduction in gate count, respectively, amongst the existing architectures. Moreover, power saving of 55% and 32% can be achieved for the proposed folded and fully-parallel architectures, respectively, where they can process 60 fps of 4K and 30 fps of 8K UHD video sequences in 300 MHz operating frequency.

FINDER: Find Efficient Parallel Instructions for ASIPs to Improve Performance of Large Applications

Application-specific instruction-set processors (ASIPs) utilize customized instructions to speedup a specific application or a set of applications. Thus, ASIPs execute the application(s) faster and are energy efficient compared to general-purpose processors. State-of-the-art custom instruction design methods typically target small applications or kernels of an application, often demanding an instruction designer's ingenuity at some point (semi-automated) to achieve design goals. In this article, for the first time, a fully automated system called FINDER is presented, which finds parallel instructions for ASIPs to improve the performance of large applications and generate FLIX (flexible instructions extension instructions, which are VLIW-type instructions) configurations. Note that we do not synthesize accelerators to speedup. We demonstrate that the proposed method scales well when applied to large applications. The proposed method described in this article models parallel instructions as a graph, analyzes the graph, and finds maximum weighted cliques to create FLIX configurations for a given application. Moreover, hardware reuse within multiple FLIX configurations is incorporated into the methodology. From the configurations, a commercial processor design tool (Xtensa) creates the FLIX instructions and integrates it into a base processor. The results show that the FINDER methodology generates FLIX configurations which shows speedups of up to 2.1× for large applications and 2.7× for smaller applications when compared to the base processor (without FLIX instructions). The logic area increase on average is 11%, and in the worst case is 22%. The energy-delay product can be up to 7.3× lower than when the application is executed on the base processor. Compared to the state-of-the-art systems which are typically demonstrated on applications with less than 100 lines of code, FINDER is capable of analyzing applications with thousands of lines of code and can automatically generate instructions for such applications.