Abstract
This paper presents a new hardware reconfiguration approach named hardware reconfiguration through digital television (HARD), which can update FPGA hardware modules based on digital TV (DTV) signals. Such a scheme allows several synthesized hardware cores (bitstreams) signaled and broadcast through open DTV signals via data streaming to be identified, acquired, decoded, and then used for system updates. Reconfiguration data are partitioned, encapsulated into private sections, and then sent in a carrousel fashion in order to be recovered by modified receivers. Service information content, specially designed for identifying and describing the characteristics of multiplexed hardware bitstreams, was added to the transmitted signal and provided all necessary information in the traditional DTV style. The receiver framework, in turn, checked whether those characteristics corresponded to its embedded reconfigurable devices and, if a match was found, it reassembled the related bitstreams and reconfigured the respective internal circuits. Experiments performed with an implementation of the proposed methodology confirmed its feasibility and showed that remounting and reconfiguration times were satisfactory and presented no blocking aspect. Finally, HARD can be used in several designs regarding intelligent reconfigurable devices, minimize device costs in the long term, and provide better hardware reuse.
Highlights
Embedded systems and digital TV (DTV) receivers are designed with no concern for technology advancements regarding computational tasks performed by hardware over time
Four VHDL and Verilog examples were used, which were synthesized for a reference FPGA and tested and validated employing an EDA tool
This work presents a new approach for hardware reconfiguration, which is intended to be used in DTV environments
Summary
Embedded systems and digital TV (DTV) receivers are designed with no concern for technology advancements regarding computational tasks performed by hardware over time. One may notice that AVC/H.264-based systems cannot immediately incorporate the benefits of HEVC due to legacy hardware Such flexibility could be achieved if DTV receivers could perform tasks through reconfigurable devices (e.g., a field-programmable gate array (FPGA)) instead of ASICs. Currently, the semiconductor industry and open core communities have boosted the use of FPGAs. It is worth noticing that they even provide hardware description source codes (e.g., VHSIC hardware description language (VHDL) [7] and Verilog [8]) for many applications (e.g., crypto cores, DSP cores, and encoder/decoder cores), which are available for download and immediate use in project solutions [9]. It is expected that the subject of this work, along with its related schema, can stimulate the scientific community to develop a wide range of environments which rely on hardware update technologies
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