Hardware Resource Utilization Research Articles

Comp-TCAM: An Adaptable Composite Ternary Content-Addressable Memory on FPGAs

Field-programmable gate arrays (FPGAs) having software-like reconfigurability and hardware-like performance are adopted as developing platforms to implement complex systems, i.e., software-defined networks (SDNs). Ternary content-addressable memory (TCAM) is not present in modern FPGA, but rather it is used as a softcore where needed. The hardware structure of an FPGA is flexible but rigid; the elemental structure is fixed and can be used in a limited number of ways. Existing FPGA-based TCAMs exhaust one particular type of memory when a large size is implemented, resulting in a shortage of memory for the rest of the system. Our proposed architecture uses only those memory elements of FPGA that are redundant and not used by other parts. In this letter, the proposed architecture, comp-TCAM, combines both block RAM (BRAM) and lookup table RAM (LUTRAM) to implement the TCAM architecture; that eliminates the dependency on the type of memory and is adaptable to the requirement of the system. Evaluation results show the feasibility, scalability, and effectiveness of the proposed TCAM architecture compared to the existing TCAM architectures. The hardware resource utilization on Xilinx VIrtex-7 FPGA is reduced by 41.6% compared to state-of-the-art FPGA-based TCAM with no harm to the system’s performance providing a throughput of 21.06 Gbits/s.

Load Balancing Optimization of In-Memory Database for Massive Information Processing of Internet of Things (IoTs)

Based on the analysis of the key technologies of the Internet of Things service platform architecture, a load balancing optimization scheme of in-memory database based on the massive information processing of the Internet of Things service platform is proposed. This scheme firstly proposes a system model that can satisfy the mass sensor information processing under the open platform environment and designs several functional unit modules of the system. By combining these functional units, the service can be configured for thousands of services and tenants. This paper presents an adaptive strategy selection method, which can automatically select the optimization strategy by dividing the position and querying the selection rate to improve the efficiency of the adaptive index algorithm. The index structure is initialized by parallel sorting algorithm, and the query statement is executed and the index structure is optimized by thread level parallel and radix sort methods. An elastic pipeline technique is proposed, which includes an elastic iterator model and a dynamic scheduler. The elastic iterator model is an upgrade of the traditional iterator model, adding the characteristics of dynamic multicore execution. In the process of query processing, dynamic scheduler monitors the load of each node in real time and dynamically adjusts the parallelism, so as to realize the load balance of in-memory database and maximize the utilization of hardware resources. The elastic pipeline realizes the isolation of parallelism from query compilation to avoid inappropriate parallelism allocation caused by missing and insufficient information during query compilation.

Unified Posit/IEEE-754 Vector MAC Unit for Transprecision Computing

Transprecision computing targets energy-efficiency with multiple floating-point modules with different precisions to suit application requirements. Variable-precision architectures aim at making a more efficient hardware resource utilization, but they often rely on the IEEE-754 standard, without low-precision arithmetic support. Alternatively, the Posit format is particularly well-suited for low-precision arithmetic. However, for higher precisions, hardware requirements become prohibitive. Accordingly, this brief proposes a new unified Posit/IEEE-754 Vector Multiply-Accumulate (VMAC) unit, comprising a vectorized variable-precision datapath with shared support for the Posit and IEEE-754 formats. A 28nm ASIC implementation resulted in 50&#x0025; less area and <inline-formula> <tex-math notation="LaTeX">$2.9\times $ </tex-math></inline-formula> less power consumption than typical transprecision setups.

Fixed-Point Analysis and FPGA Implementation of Deep Neural Network Based Equalizers for High-Speed PON

Adeep neural network based equalizer is proposed to mitigate the intersymbol interference observed in next generation high speed passive optical network (PON) links. The DNN based equalizer is shown to outperform the best known conventional equalizer, the maximum likelihood sequence estimator (MLSE) both in back-back and through fiber experiments. To reduce the hardware complexity of DNN based equalizer for PON systems, we investigate the use of embedded parallelization within a DNN structure having multiple symbol outputs from one DNN. We further investigate using a classification output stage with cross entropy cost to perform joint decision on multiple symbol outputs and demonstrated that the sensitivity gain of such scheme over regression output. To understand the complexity of hardware implementation, the fixed-point DNN based equalizers are developed and implemented in FPGA. The impact of fixed-point resolution on the receiver sensitivity and hardware resource utilization in FPGA implementation is analyzed and reported in detail. We show that a reduction of over 40% in LUTs (look up table) utilization is possible by reducing the DNN's weight resolution from 8-bit to 4-bit while incurring a small penalty in receiver sensitivity.

An Area-Efficient FPGA Implementation of a Real-Time Multi-Class Classifier for Binary Images

Developing image classification modules in embedded systems is a complex task due to the limited resources available. In this brief, a multi-class image classifier using HOG feature extractor and SVM classifier is proposed for binary images. The novelty of the proposed system is applying two steps of binarization to the HOG technique to improve processing speed and area efficiency. First, HOG features are extracted from binary images to simplify the feature extraction process. Second, block normalization of the HOG is replaced with binarization to reduce hardware resource utilization. Compared to a similar existing work, our system speeds up the classification process while utilizing fewer hardware resources, with an 11.4% higher classification accuracy using the same setting.

A two-stage adaptive thresholding segmentation for noisy low-contrast images

Image recognition is the process of recognizing and classifying objects with machine learning algorithms. Image binarization is the first and most challenging step in image recognition, in which foreground objects are separated from their background. When foreground objects have complex morphological structure and background noise is strong, foreground objects are often being fractured into subcomponents. To address the over-segmentation issue of organisms with complex structures, we propose a 2-stage adaptive binarization approach based on Sauvola's binarization algorithm. We tested the effectiveness of the new approach on a set of underwater images with jellyfish collected in nearshore waters using a shadowgraph underwater plankton imaging system, PlanktonScope, because jellyfish have relatively complex structure and are often over-segemented. The results showed that the 2-stage approach improved the integrity of extracted jellyfish compared to traditional binarization methods, including Sauvola's algorithm. The analysis of local entropy values showed that the first stage effectively suppresses redundant information in the image and reduces the number of Region of Interests (ROIs), and the second stage preserves relatively weak and low-intensity signals to ensure the integrity of the extracted targets. The 2-stage approach improves hardware resource utilization and computational efficiency. It is robust for images acquired in sub-optimal conditions and enhances the accuracy of analytical results in the study of marine organisms using imaging systems.

High-throughput, area-efficient hardware architecture of CABAC-Binarization for UHD applications

Video compression imposes a high throughput requirement on the latest video encoders (HEVC and VVC), and CABAC is primarily used entropy method in such applications. Binarization is first and vital sub-block of CABAC that requires high throughput and better performance. A high-throughput and area-efficient Binarization has been proposed in this work. A parallel processing hardware architecture is used, which processes five input symbols per clock cycle and probability estimation to obtain high throughput. The resource sharing technique is used to optimize the utilization of hardware resources. Further, a pairing-SEs scheme and storage buffers have been incorporated in the data path for better performance. The Binarization architecture is designed in Verilog HDL and verified on Artix-7 FPGA. It is also implemented on ASIC using 90 nm technology. The proposed design achieved a maximum throughput of 3.14 Gbin/s at 282 MHz and consumed considerably low hardware area as compared to other architectures. The proposed Binarization is adaptive, scalable, and versatile in functionality.

B2-Tree: Page-Based String Indexing in Concurrent Environments

Recently proposed index structures, that combine trie-based and comparison-based search mechanisms, considerably improve retrieval throughput for in-memory database systems. However, most of these index structures allocate small memory chunks when required. This stands in contrast to block-based index structures, that are necessary for disk-accesses of beyond main-memory database systems such as Umbra. We therefore present the B2-tree. The outer structure is identical to that of an ordinary B+-tree. It still stores elements in a dense array in sorted order, enabling efficient range scan operations. However, B2-tree is composed of multiple trees, each page integrates another trie-based search tree, which is used to determine a small memory region where a sought entry may be found. An embedded tree thereby consists of decision nodes, which operate on a single byte at a time, and span nodes, which are used to store common prefixes. This architecture usually accesses fewer cache lines than a vanilla B+-tree as shown in our performance evaluation. As a result, the B2-tree answers point queries considerably faster. Concurrent access to B2-tree pages are managed by an optimistic locking protocol which results in high utilization of the available hardware resources. Our evaluation of read-write workloads attests more than competitive performance for the B2-tree compared to a traditional B+-tree.

An Efficient UD Factorization Implementation of Kalman Filter for RTK Based on Equivalent Principle

Real-time kinematic (RTK) is a technique frequently utilized to provide real-time highly precise positioning services for mobile Internet-of-Things (IoT)-embedded terminals from intelligence appliances and smartphones to autonomous drones and self-driving vehicles. To fully utilize hardware resources, the internal GNSS chips or modules equipped in IoT terminals should satisfy the traits of energy efficiency and low computational complexity. As the number of global navigation satellite system (GNSS) increases, the continuous accumulation of high-dimensional rounding errors, the rough system model, and seriously distorted observations will result in divergence and considerable processing burden in the conventional Kalman filter (KF) process. Computational efficiency is significant in the reduction in the power consumption and intensifies the positioning performance of GNSS receivers. Here, a new filter strategy based on UD factorization, where U stands for the unit upper-triangular factor and D indicates the diagonal factor, is proposed for RTK positioning to enhance the numerical stability and reduce the computational effort. The equivalent principle was applied to turn double-difference (DD) observations into zero-difference (ZD) observations. Then, the UD-factorization-based Kalman filter (UD-KF) is proposed as a way to sequentially provide accurate real-time estimations of the filter states and variance–covariance (VC) matrix. Both static and dynamic tests were carried out with single-frequency data from a GPS to evaluate the performance of UD-KF. The results of the zero-baseline test show that UD-KF can obtain smaller RMS of the estimated parameters as the noise of DD observations was twice that of the ZD observations. A short baseline test showed that, compared to the regular filter approach with DD observations, UD-KF achieved a shorter computation time with a higher data utilization rate for both filtering and fixing stages, with an average improvement of 32% and 18%. Finally, a dynamic test showed that the UD-KF can avoid the undesirable effect of satellite changes. Therefore, compared to KF with DD observations, the UD-KF with equivalent ZD observations can enhance the robustness as well as improve the positioning accuracy of RTK positioning.

An Efficient Full Hardware Implementation of Extended Merkle Signature Scheme

This paper presents a full hardware implementation of the eXtended Merkle Signature Scheme (XMSS), a NIST approved and IETF RFC specified post-quantum cryptography (PQC) algorithm. An optimized node traversal is proposed to enable efficient memory utilization without compromising the computational latency of the L-tree and Merkle tree construction, which are two key components used for the compression of the Winternitz One-Time Signature (WOTS) public key in XMSS. The computation of the authentication path during signature generation has also been significantly sped up by our proposed hardware implementation of the Buchmann, Dahmen, and Schneider (BDS) algorithm. Our implementation has completely avoided the use of block random-access memory, which is known to be vulnerable to side-channel attacks. The memory requirement has been highly optimized for implementation with small flip-flop chains and register counters as pointers for fast data access. To the best of our knowledge, this is the first full hardware implementation of all three <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">key generation</i> , <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">signing</i> and <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">verification</i> operations of XMSS. The design has been prototyped and evaluated on a 28 nm FPGA platform to demonstrate its performance improvements over the most efficient software and hardware/software co-design methods reported to date. Specifically, it increases the computational efficiency of the best reported XMSS implementation for <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">key generation</i> and <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">signature generation</i> by about 20% and 50%, respectively. It can also run at 10% higher clock speed than the fastest hardware implementation of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">signature verification</i> in FPGA with 8% lower hardware resource utilization.

Hardware Implementation of Stockwell Transform and Smoothed Pseudo Wigner Ville Distribution Transform on FPGA using CORDIC Algorithm

A comparison of linear and quadratic transform implementation on field programmable gate array (FPGA) is presented. Popular linear transform namely Stockwell Transform and Smoothed Pseudo Wigner Ville Distribution (SPWVD) transform from Quadratic transforms is considered for the implementation on FPGA. Both the transforms are coded in Verilog hardware description language (Verilog HDL). Complex calculations of transformation are performed by using CORDIC algorithm. From FPGA family, Spartan-6 is chosen as hardware device to implement. Synthetic chirp signal is taken as input to test the both designed transforms. Summary of hardware resource utilization on Spartan-6 for both the transforms is presented. Finally, it is observed that both the transforms S-Transform and SPWVD are computed with low elapsed time with respect to MATLAB simulation.

GPU-accelerated and pipelined methylation calling.

The third-generation DNA sequencing technologies, such as Nanopore Sequencing, can operate at very high speeds and produce longer reads, which in turn results in a challenge for the computational analysis of such massive data. Nanopolish is a software package for signal-level analysis of Oxford Nanopore sequencing data. Call-methylation module of Nanopolish can detect methylation based on Hidden Markov Model (HMM). However, Nanopolish is limited by the long running time of some serial and computationally expensive processes. Among these, Adaptive Banded Event Alignment (ABEA) is the most time-consuming step, and the prior work, f5c, has already parallelized and optimized ABEA on GPU. As a result, the remaining methylation score calculation part, which uses HMM to identify if a given base is methylated or not, has become the new performance bottleneck. This article focuses on the call-methylation module that resides in the Nanopolish package. We propose Galaxy-methyl, which parallelizes and optimizes the methylation score calculation step on GPU and then pipelines the four steps of the call-methylation module. Galaxy-methyl increases the execution concurrency across CPUs and GPUs as well as hardware resource utilization for both. The experimental results collected indicate that Galaxy-methyl can achieve 3×-5× speedup compared with Nanopolish, and reduce the total execution time by 35% compared with f5c, on average. The source code of Galaxy-methyl is available at https://github.com/fengyilin118/.

FPGA Acceleration of 3GPP Channel Model Emulator for 5G New Radio

The channel model is by far the most computing intensive part of the link level simulations of multiple-input and multiple-output (MIMO) fifth-generation new radio (5G NR) communication systems. Simulation effort further increases when using more realistic geometry-based channel models, such as the three-dimensional spatial channel model (3D-SCM). Channel emulation is used for functional and performance verification of such models in the network planning phase. These models use multiple finite impulse response (FIR) filters and have a very high degree of parallelism which can be exploited for accelerated execution on Field Programmable Gate Array (FPGA) and Graphics Processing Unit (GPU) platforms. This paper proposes an efficient re-configurable implementation of the 3rd generation partnership project (3GPP) 3D-SCM on FPGAs using a design flow based on high-level synthesis (HLS). It studies the effect of various HLS optimization techniques on the total latency and hardware resource utilization on Xilinx Alveo U280 and Intel Arria 10GX 1150 high-performance FPGAs, using in both cases the commercial HLS tools of the producer. The channel model accuracy is preserved using double precision floating point arithmetic. This work analyzes in detail the effort to target the FPGA platforms using HLS tools, both in terms of common parallelization effort (shared by both FPGAs), and in terms of platform-specific effort, different for Xilinx and Intel FPGAs. Compared to the baseline general-purpose central processing unit (CPU) implementation, the achieved speedups are 65X and 95X using the Xilinx UltraScale+ and Intel Arria FPGA platform respectively, when using a Double Data Rate (DDR) memory interface. The FPGA-based designs also achieved ~3X better performance compared to a similar technology node NVIDIA GeForce GTX 1070 GPU, while consuming ~4X less energy. The FPGA implementation speedup improves up to 173X over the CPU baseline when using the Xilinx UltraRAM (URAM) and High-Bandwidth Memory (HBM) resources, also achieving 6X lower latency and 12X lower energy consumption than the GPU implementation.

Open Loop Synchronization Techniques Benchmarking for Distributed Energy Sources Connection

Synchronization is a crucial process in the operation of grid-connected distributed energy sources. Synchronization techniques are classified in closed-loop (CLS) and open-loop synchronization (OLS) techniques. Unlike the CLS technique, OLS techniques are recent and less known. This paper discusses a comparative analysis of the three prominent state-of-the-art OLS techniques. Accordingly, a benchmark model is proposed to systematically evaluate the performance of the OLS techniques under grid voltage disturbances such as harmonic distortions, voltage unbalance, DC offset, and low voltage ride through operation. Given the hardware resource utilization, the computational complexity and the execution time are also presented to judge the efficacy of the proposed model. Thus, engineers/or researchers can better understand the choice of hardware resources and the preferred dynamic performance of a synchronization scheme applied to control and protect a grid-tied power converter. Simulation and experimental results are presented and discussed to demonstrate the purpose of the proposed model.

ReAAP: A Reconfigurable and Algorithm-Oriented Array Processor with Compiler-Architecture Co-Design

Parallelism and data reuse are the most critical issues for the design of hardware acceleration in a deep learning processor. Besides, abundant on-chip memories and precise data management are intrinsic design requirements because most of deep learning algorithms are data-driven and memory-bound. In this paper, we propose a compiler-architecture co-design scheme targeting a reconfigurable and algorithm-oriented array processor, named ReAAP. Given specific deep neural networks, the proposed co-design scheme is effective to perform parallelism and data reuse optimization on compute-intensive layers for guiding reconfigurable computing in hardware. Especially, the systemic optimization is performed in our proposed domain-specific compiler to deal with the intrinsic tensions between parallelism and data locality, for the purpose of automatically mapping diverse layer-level workloads onto our proposed reconfigurable array architecture. In this architecture, abundant on-chip memories are software-controlled and its massive data access is precisely handled by compiler-generated instructions. In our experiments, the ReAAP is implemented on an embedded FPGA platform. Experimental results demonstrate that our proposed co-design scheme is effective to integrate software flexibility with hardware parallelism for accelerating diverse deep learning workloads. As a whole system, ReAAP achieves a consistently high utilization of hardware resource for accelerating all the diverse compute-intensive layers in ResNet, MobileNet, and BERT.

Smart Communication Using 2D and 3D Mesh Network-on-Chip

Network on chip (NoC) is an integrated communication system on chip (SoC), efficiently connecting various intellectual property (IP) modules on a single die. NoC has been suggested as an enormously scalable solution to overcome the communication problems in SoC. The performance of NoC depends on several aspects in terms of area, latency, throughput, and power. In this paper, the 2D and 3D mesh NoC performance on Virtex-5 field-programmable gate array (FPGA) is studied. The design is carried in Xilinx ISE 14.7 and the behavior model is followed based on XY and XYZ routing for 2D and 3D mesh NoC respectively. The functional simulation is performed on Modelsim 10.0 software. The on-chip communicationis verified for 2D and 3D mesh NoC with different cluster sizes that pre-estimates the hardware resources utilization on FPGA. The algorithm provides a substantial platform to NoC designers to overcome the issues of substantial configuration in NoC synthesis on FPGA in case of multiple processing elements, routers, cache controllers are integrated with SoC. The suggested NoC is helpful for the embedded system design of smart wireless communication.

A Sparse Neural Network-Based Power Adaptive DPD Design and Its Hardware Implementation

In this paper, an efficient neural-network-based adaptive DPD design which performs well under power varying conditions is presented. The DPD design is derived on the basis of the envelop time-delay neural network (ETDNN). The redefined ETDNN-DPD requires the part of parameter updates, which enables to adapt it to the rapid change of power amplifier (PA) distortion. Additionally, the redefined ETDNN-DPD also maintains the stability of the compensation performances under varying power condition while its structure is pruned by the structured pruning. Furthermore, to verify its practical use, we also propose the weight scaling technique, which reduces multiplications of the redefined ETDNN-DPD, and applied it to the implementation of the redefined ETDNN-DPD on FPGA. Compared FPGA-implemented ETDNN-DPD with FPGA-implemented conventional memory polynomial DPD, we verified that our proposed DPD achieved 3.2 dB better error vector magnitude (EVM) while lower hardware resource utilization at the fixed power level. Moreover, our proposed DPD kept better performance under the varying power condition only by the partial update of its parameters than memory polynomial DPD.

Design and analysis of hardware Trojans in approximate circuits

Approximate computing can accept errors in computation systems to achieve better utilisation of hardware resources. Approximate computing has been successfully developed in integrated circuits, such as approximate arithemtic circuits and approximate accelerators. Unfortunately, recent works show that approximate circuits also have security vulnerabilities. Hardware Trojan is one of the biggest threats to hardware security. However, very limited research has been conducted on hardware Trojans in approximate circuits. In this letter, two types of hardware Trojans, namely Function-destructive Trojans and Information-leaking Trojans, are presented. The Trojans are designed based on the characteristics of approximate circuits. The effectiveness of the hardware Trojans are analysed using the evaluation metrics for approximate circuits.

RDO-WT: optimised Wallace Tree multiplier based FIR filter for signal processing applications

ABSTRACT Digital Signal Processing (DSP) and communication applications utilise a Finite Impulse Response (FIR) filter which is key component for digital communication. Moreover, quality of signal is enhanced by FIR filter which is mostly employed by filtering applications. The execution speed of the FIR is determined by multiplier’s performance. Hardware resource utilisation and speed-up operations are some of the issues found in existing methods which are occurred due to a critical path in incomplete products. So, this can be improved by the proposed optimisation algorithm based multiplier. This research establishes the execution of FIR Filter design using Red Deer Optimisation (RDO) based Wallace Tree (WT) multiplier. By using the optimised WT multiplier, FIR filter is simulated to examine the area, delay, power and frequency for different tap FIR filter. Moreover, FIR filter with optimised WT is introduced to perform signal denoising application. Proposed multiplier design is simulated using Xilinx tool. Filtering simulation is done by using the publicly available database named as MIT-BIH database and the noise removal process is simulated using Matlab tool. The FIR filter designed with proposed multiplier provides delay around 1.373 ns and consumes 0.143 W as total power which is lesser than the existing methods.

Design and FPGA Verification of Custom-Shaped Chaotic Attractors Using Rotation, Offset Boosting and Amplitude Control

This brief proposes a method of generating custom-shaped attractors, which depends on a planarly rotating V-shape multi-scroll chaotic system with offset boosting and amplitude control, and its FPGA verification. The proposed planarly rotating, translational (offset boostable), and scalable (amplitude controllable) system exhibits a wide basin of attraction and can cover the whole space. Consequently, non-autonomous parameters enable generating attractors of custom-shapes, e.g., letters of the English alphabet as a demonstrating example. Furthermore, non-autonomous parameters are employed to generate attractors with the shape of complete words and sentences. This takes place by generating letter shapes successively and controlling the position and size of each letter. The chaotic behavior is quantified and indicated using spectral entropy. Experimental verification on FPGA shows good hardware resources utilization and throughput.