Hardware Realization Research Articles

Efficient Hardware Realization of SC Polar Decoders Using Compound Pipelined Processing Units and Auxiliary Registers

Efficient Hardware Realization of SC Polar Decoders Using Compound Pipelined Processing Units and Auxiliary Registers

Hardware realization of collision avoidance method in VLF-LF frequency bands in mine conditions

Hardware realization of collision avoidance method in VLF-LF frequency bands in mine conditions

Novel neuromorphic architectures based on crossbar arrays of (Co-Fe-B)<sub>x</sub>(LiNbO<sub>3</sub>)<sub>100−x</sub> nanocomposite memristors

Memristor-based neuromorphic computing systems (NСSs) provide a fast, high computational and energy efficient approach to neural network (NN) training and solving cognitive problems (pattern recognition, big data processing, prediction, etc.) [1]. Memristors could be organized in large crossbar arrays to perform vector-matrix multiplication (VMM) in a natural one-step way by the weighted electrical current summation (according to the Ohm’s and Kirchhoff’s laws) [1]. In contrast, being the most massively parallel operation in NN learning and inference, VMM is extremely time- and energy-expensive in traditional von Neumann architectures. Owing to this difference, memristor-based NCSs are of high interest. Memristors have already been successfully implemented for diverse NCS realizations, and such schemes as multi-layer perceptron (MLP) [2], long short-term memory and others have been demonstrated. Most of these NCSs are usually trained by various types of gradient descent learning algorithm, the hardware realization of which is challenging due to unreliable cycle-to-cycle (c2c) and device-to-device (d2d) variations of memristive devices. Several approaches have been proposed to partially mitigate these problems, including reservoir computing [3] and fine feature engineering [4]. The general idea of such approaches is to reduce the number of required weights (i.e. memristors) compared with fully connected NNs. In this respect, such novel architectures as convolutional NN (CNN) and MLP-mixer are of high interest as they provide significant weight reduction without classification efficiency drop. Although CNN based on memristors was already demonstrated, different aspects of its realization (such as hybrid hardware-software co-design) have yet to be studied. MLP-mixer was realized only in software. Therefore, in this work we have studied the possibility of hardware realization of CNN and MLP-mixer networks based on crossbar arrays of memristors. For this purpose, we studied (Co-Fe-B)x(LiNbO3)100−x nanocomposite (CFB-LNO NC) memristors, which operate through a multifilamentary resistive switching (RS) mechanism, demonstrate high endurance, long retention and possess multilevel RS [5]. Crossbar array of memristors was fabricated using laser photolithography for patterning electrode buses and ion-beam sputtering on the original facility for active layer deposition (~10 nm thick LiNbO3 and ~290 nm thick CFB-LNO NC with x ≈10–25 at.%). Details of the fabrication process could be found elsewhere [5]. I-V curves of the fabricated memristors showed small c2c and d2d variations, plasticity with 16 different resistive states and endurance of more than 105 cycles. Using the nanocomposite based crossbar arrays, we implemented a hybrid CNN, consisting of a hardware feature extractor with one/two kernels and a software classifier. Additionally, we have demonstrated in simulation that the usage of the memristors under study in the accurately adapted MLP-Mixer architecture results in high classification accuracy that is resilient to memristive variations and stuck devices.

Vector-switched digital predistortion for concurrent dual-band transmitters with hybrid time-division multiplexing scheme

In a concurrent dual-band digital predistortion (DPD) system, due to the large number of two-dimensional (2D) polynomial-based model coefficients and the existence of cross-modulation terms, the hardware realization usually requires a lot of resources. To alleviate this problem, this paper proposes a hardware-efficient field programmable gate array (FPGA)-based piecewise vector-switched (PVS) DPD method. With the PVS method, a 2D memory polynomial (MP) model with fewer coefficients can be used as a sub predistorter model for each region. Furthermore, a new hybrid time-division multiplexing (HTDM) scheme is proposed for the 2D-MP predistorter architecture, which enables sharing of cross-modulated lookup tables (LUTs) and complex multipliers in a hybrid way. Experimental results show that the proposed method improves the adjacent channel power ratio (ACPR) and normalized mean square error (NMSE) by 18.74 dB and 13.23 dB, respectively, and saves about 30% and 80% of RAM and DSP resources, respectively.

Theoretical study and circuit implementation of three chain-coupled self-driven Duffing oscillators.

In this paper, we describe the scenario from the birth of oscillations to multi-spiral chaos in a novel system composed of three chain-coupled self-driven Duffing oscillators. Eight of the equilibrium points develop (multiple) Hopf bifurcation when varying a parameter (e.g., coupling coefficient). Considering the computer integration of the state equations, the combined exploitation of Lyapunov exponent plots, bifurcation diagrams, basins of attraction, and phase portraits, unusual and attractive features were highlighted including the coexistence of eight bifurcation branches, Hopf bifurcations, a multitude of coexisting types of oscillations and a six-spiral chaotic attractor, just to cite a few. Using basic electronic components, the electronic circuit of the three chain-coupled Duffing oscillator system is performed. Orcad-PSpice simulated dynamics of the proposed chain-coupled analog circuit confirm the theoretically disclosed features. Moreover, the practical feasibility of the coupled system is demonstrated by considering microcontroller-based hardware realization.

Spiking Neurons with Neural Dynamics Implemented Using Stochastic Memristors

AbstractImplementing and integrating spiking neurons for neuromorphic hardware realization conforming to spiking neural networks holds great promise in enabling efficient learning and decision‐making. The spiking neurons, however, may lack the spiking dynamics to encode the dynamical information in complex real‐world problems. Herein, using filamentary memristors from solution‐processed hexagonal boron nitride, this study assembles leaky integrate‐and‐fire spiking neurons and, particularly, harnesses the common switching stochasticity feature in the memristors to allow key neural dynamics, including Poisson‐like spiking and adaptation. The neurons, with the dynamics fitted via hardware‐algorithm codesign, suggest a potential in realizing spike‐based neuromorphic hardware capable of handling complex problems. Simulation of an autoencoder for anomaly detection of time‐series real analog and digital data from physical systems is demonstrated, underscoring its promising prospect in applications, especially, at the edges with limited computation resources, for instance, auto‐pilot, manufacturing, wearables, and Internet of things.

Analysis of neural network connections based on memristors and their multiple offset phenomena

The article suggests a construction method of a magnetron memristor connecting a three-dimensional Hopfield neural network and a Rulkov neuron in order to build a more complex and achieve more bio-like neural network properties, which has rarely been proposed before. It is discovered that the dynamical behavior of this high-dimensional neural network system is rich, and that the system exhibits many dynamical behaviors depending on the parameter changes. It is possible to change the attractor’s amplitude and its offset boosting behavior by varying various parameters. Changing the system parameters and modifying the system’s initial value may result in initial offset boosting behavior. Combining nonlinear dynamics research methodologies, such as phase diagram, bifurcation diagram, Lyapunov exponential spectrum, and time series diagram, demonstrates the system’s complex dynamical behavior. By analyzing the system complexity and random sequence test, we found that the system has the characteristics of large complexity and strong pseudo-randomness. Eventually, the hardware realizability is proved by the construction of the DSP platform.

Design and Performance Analysis of Hardware Realization of 3GPP Physical Layer for 5G Cell Search

5G Cell Search (CS) is the first step for user equipment (UE) to initiate communication with the 5G node B (gNB) every time it is powered ON. In cellular networks, CS is accomplished via synchronization signals (SS) broadcasted by gNB. 5G 3rd generation partnership project (3GPP) specifications offer a detailed discussion on the SS generation at gNB, but a limited understanding of their blind search and detection is available. Unlike 4G, 5G SS may not be transmitted at the center of carrier frequency, and their frequency location is unknown to UE. In this work, we demonstrate the 5G CS by designing 3GPP compatible hardware realization of the physical layer (PHY) of the gNB transmitter and UE receiver. The proposed SS detection explores a novel down-sampling approach resulting in a 60% reduction in on-chip memory and 50% lower search time. Via detailed performance analysis, we analyze the functional correctness, computational complexity, and latency of the proposed approach for different word lengths, signal-to-noise ratio (SNR), and down-sampling factors. We demonstrate end-to-end 5G CS using GNU Radio-based RFNoC framework on the USRP-FPGA platform and achieve 66% faster SS search compared to software. The 3GPP compatibility and demonstration on hardware strengthen the commercial significance of the proposed work.

Retracted: Hardware Realization of Kinematic Mechanism and Control System of Multifunctional Industrial Robot

Retracted: Hardware Realization of Kinematic Mechanism and Control System of Multifunctional Industrial Robot

Artificial neural networks for photonic applications—from algorithms to implementation: tutorial

This tutorial–review on applications of artificial neural networks in photonics targets a broad audience, ranging from optical research and engineering communities to computer science and applied mathematics. We focus here on the research areas at the interface between these disciplines, attempting to find the right balance between technical details specific to each domain and overall clarity. First, we briefly recall key properties and peculiarities of some core neural network types, which we believe are the most relevant to photonics, also linking the layer’s theoretical design to some photonics hardware realizations. After that, we elucidate the question of how to fine-tune the selected model’s design to perform the required task with optimized accuracy. Then, in the review part, we discuss recent developments and progress for several selected applications of neural networks in photonics, including multiple aspects relevant to optical communications, imaging, sensing, and the design of new materials and lasers. In the following section, we put a special emphasis on how to accurately evaluate the complexity of neural networks in the context of the transition from algorithms to hardware implementation. The introduced complexity characteristics are used to analyze the applications of neural networks in optical communications, as a specific, albeit highly important example, comparing those with some benchmark signal-processing methods. We combine the description of the well-known model compression strategies used in machine learning, with some novel techniques introduced recently in optical applications of neural networks. It is important to stress that although our focus in this tutorial–review is on photonics, we believe that the methods and techniques presented here can be handy in a much wider range of scientific and engineering applications.

Crossbar operation of BiFeO3/Ce–CaMnO3 ferroelectric tunnel junctions: From materials to integration

Ferroelectric Tunnel Junctions (FTJs) are a candidate for the hardware realization of synapses in artificial neural networks. The fabrication process for a 784 × 100 crossbar array of 500 nm large FTJs, exhibiting effective On/Off currents ratio in the range 50–100, is presented. First, the epitaxial 4 nm-BiFeO3/Ca0.96Ce0.04MnO3//YAlO3 is combined with Ni electrodes. The oxidation of Ni during the processing affects the polarity of the FTJ and the On/Off ratio, which becomes comparable to that of CMOS-compatible HfZrO4 junctions. The latter have a wider coercive field distribution: consequently, in test crossbar arrays, BiFeO3 exhibits a smaller cross-talk than HfZrO4. Furthermore, the relatively larger threshold for ferroelectric switching in BiFeO3 allows the use application of half-programming schemes for supervised and unsupervised learning. Second, the heterostructure is combined with W and Pt electrodes. The design is optimized for the controlled collapse chip connection to neuromorphic circuits.Graphical abstract

Edge learning using a fully integrated neuro-inspired memristor chip.

Learning is highly important for edge intelligence devices to adapt to different application scenes and owners. Current technologies for training neural networks require moving massive amounts of data between computing and memory units, which hinders the implementation of learning on edge devices. We developed a fully integrated memristor chip with the improvement learning ability and low energy cost. The schemes in the STELLAR architecture, including its learning algorithm, hardware realization, and parallel conductance tuning scheme, are general approaches that facilitate on-chip learning by using a memristor crossbar array, regardless of the type of memristor device. Tasks executed in this study included motion control, image classification, and speech recognition.

Hardware Realization of an Innovative Disturbance Detection Algorithm for Control Strategy of Solid-State Transfer Switch

An accurate and fast Solid-State Transfer Switch (SSTS) has the potential to automate conventional utility network. Presently, It consumes most of the transfer time in detecting the condition for initiating the transfer process. Recent developments in the power semiconductor devices technology have reduced the switching time to the tune of nanoseconds. Hence, time consumed by the disturbance detection is significant in SSTS. IEEE Std. 1100-2005 and IEEE Std. 446-1995 requires fast load transfer for SSTS. Realization of an innovative machine learning technique is implemented on three AVR microcontrollers for each of three phases. The microcontroller executes segmentation of acquired signal and calculates derivative of each segment. From each pre-processed 10-sample segment, mean absolute deviation (MAD) and energy (E) features are extracted. On the basis of feature values, SVM classifier with the linear kernel detects disturbance. Logical OR gate generates transfer enable signal to initiate the transfer process. Results of case studies appreciate the ability of proposed hardware to detect common disturbances in power system under different operating conditions. The hardware provides a feasible solution for solid state transfer switch with required accuracy and speed.

A Physical Description of the Variability in Single‐ReRAM Devices and Hardware‐Based Neuronal Networks

Resistive switching devices are candidates to be used as weight for the future hardware realization of neuronal networks. Herein, these resistive switches base on oxygen vacancy migration and can be toggled between different resistance states. Internal processes lead to a variability over time in these states. To understand this, a dynamical model is developed, which links the internal physical mechanism to the current response. Thereby, the electronic current is calculated by tunneling processes over oxygen vacancies. The model allows to understand the physical transport properties and the current–voltage dependence. Integrating ionic hopping processes clarifies the variability in the electronic conduction. The derived model does not require empirical input parameters and only depends on the properties of the materials. This allows to use literature values and independently compare them to electrical measurements. The model predicts the experiments correctly. Thereupon, the physical properties of the conduction are investigated with respect to the transport over discrete energy levels, which change under the hopping of oxygen vacancies. Afterwards, the current level and variability are simulated for increasing oxygen vacancy concentrations to investigate analog switching, which is required for neuronal network layers. Finally, the variability is tested with multiple interacting cells in a neuronal layer.

Artificial Neural Network Chaotic PRNG and simple encryption on FPGA

Artificial Neural Networks (ANNs) are remarkably able to fit complex functions, making them useful in various applications and systems. This paper uses ANN to fit the Pehlivan–Uyaroglu Chaotic System (PUCS) to produce an Artificial Neural Network Chaotic Pseudo-Random Number Generator (ANNC-PRNG). The proposed PRNG imitates the PUCS chaotic system’s properties and attractor shape. The proposed ANNC-PRNG is implemented in a simple image encryption system on the Xilinx Kintex-7 Genesys 2 Field Programmable Gate Array (FPGA) board. Hardware realization of an ANN trained on chaotic time series has not been presented before. The proposed ANN can be used for different numerical methods or chaotic systems, including fractional-order systems while keeping the same resources despite the methods’ complexity or chaotic systems’ complexity. Extensive testing for the ANNC-PRNG was done to prove the randomness of the produced outputs. The proposed ANNC-PRNG and the encryption system passed various well-established security and statistical tests and produced good results compared to recent similar research. The encryption system is robust against different attacks. The proposed hardware architecture is fast as it reaches a maximum frequency of 12.553 MHz throughput of 301 Mbit/s.

Design of a High Performance Vector Processor Based on RISIC-V Architecture

This paper proposes a high performance Vector processor based on the high performance Embedded Core which is named TS800. The TS800 is a 4-core processor based on RISC-V architecture, implements IMAFDV instruction set, supports L2 Cache, branch prediction, sequential pipeline, and dual-issue structure. The traditional CPU mainly supports Scalar calculations, or only supports Vector calculations. For applications such as image and signal processing, there are a large number of data parallel computing operations. To solve the problem of low performance of parallel data calculations in industrial power applications, it is proposed to add VPU hardware implementation in the TS800. The TS800 can support FFT algorithm, adaptive controllers Reinforcement learning and learning-based underlying algorithm requirements. In this paper, the module and data flow between each processing unit and the control circuit, that is, the hardware realization of VPU module are proposed. Large-area units such as float arithmetic, multiplication and division are multiplexed with the Scalar operator in the CPU, while the control circuit is placed in the VPU-ALU, and the area is small. Units such as arithmetic and logic operation instructions, shift operation instructions, comparison operation instructions, and permutation instruction are implemented through the VPU-ALU, which makes the overall design area smaller and the performance better. At the same time, through the fir, fft, conv, matrix, Signal Converge and variance test, it is proved that while executing the same program, the running time of the cpu only with Scalar is 1.44 to 9.55 times that of the CPU with Vector module, which can support the underlying algorithm of the adaptive controller.

A versatile dynamic noise control framework based on computer simulation and modeling

Abstract This article attempts to effectively reduce the impact of active noise pollution on human life, and to make up for the traditional passive noise control technique. In low-frequency noise control, there are some shortcomings. The making of active noise control (ANC) technique, in low-frequency noise reduction, can achieve very good results. This article proposes a versatile dynamic noise control framework based on computer simulation and modeling. The research is mainly focused on the principle and application of versatile dynamic noise control framework. To accomplish this, a research method combining theoretical analysis, software simulation, and hardware realization is adopted. The derivation process of the adaptive algorithm (LMS algorithm, filter-XLMS algorithm, etc.) is introduced in detail, and the influencing factors of algorithm performance, a variable step size normalization algorithm based on relative error is proposed. Perform simulation calculations on various algorithms in MATLAB, analyze parameters such as step factor, filter order, etc., and the degree of influence on the algorithm’s convergence speed and steady-state performance. Common command set software is used, the path adaptive identification is realized, and the program design of the versatile dynamic noise control framework is used. After completion of software and hardware debugging on the experimental platform of generalized comfort, the experimental equipment layout is completed. Using the additive random noise method, the adaptive offline modeling of the first path of the versatile dynamic noise control framework is realized. Finally, utilizing the experimental platform of generalized comfort, the adaptive ANC experiment of the single-channel filtered least mean square algorithm is conducted, then the experimental data are analyzed, and at last, the actual application effect of the versatile dynamic noise control framework is verified.

Reduced complexity XOR trees for LDPC codes and BS-LFSR techniques to High-Speed memory applications

Low-Density Parity Check (LDPC) Codes exhibit dominant role which deal with limitation of storage capacity. Hardware realization of Parity Check Codes is slow and consumes more power which makes it vulnerable for the light weight applications. Hence, to improve the throughput, area and power dissipation, parity check architectures must be constrained. This article proposes architecture of LDPC codes for high-speed memory applications with comparable XOR-gate tree-based VLSI design. The designed extension module includes Bit Swapping Linear Feedback Shift Register (BS-LFSR) technique that can illustrate and gauge expansion of faults in both the versions of faulty and fault-free. Furthermore, the power dissipation has been reduced by 8% and area by 83% with its extension module. This work has been designed using Vivado HLS and the hardware implementation of BS-LFSR has been verified on Zync 7000 series FPGA board for faulty and fault-free test patterns.

Efficient forecasting of chaotic systems with block-diagonal and binary reservoir computing.

The prediction of complex nonlinear dynamical systems with the help of machine learning has become increasingly popular in different areas of science. In particular, reservoir computers, also known as echo-state networks, turned out to be a very powerful approach, especially for the reproduction of nonlinear systems. The reservoir, the key component of this method, is usually constructed as a sparse, random network that serves as a memory for the system. In this work, we introduce block-diagonal reservoirs, which implies that a reservoir can be composed of multiple smaller reservoirs, each with its own dynamics. Furthermore, we take out the randomness of the reservoir by using matrices of ones for the individual blocks. This breaks with the widespread interpretation of the reservoir as a single network. In the example of the Lorenz and Halvorsen systems, we analyze the performance of block-diagonal reservoirs and their sensitivity to hyperparameters. We find that the performance is comparable to sparse random networks and discuss the implications with regard to scalability, explainability, and hardware realizations of reservoir computers.

Software Defined Radio: A Basic Hardware Realization of SDR Receiver

This paper aims to provide a general overview of SDRs, their history, need, basic operation and benefits, along with a basic hardware realization of SDR receiver using Arduino Nano microcontroller. Software Defined Radio or SDR is one of the most important technologies and is essential for a modern wireless communication system. SDRs are known for their versatility as they can be customised to operate on any frequency band, or can have different implementations of modulation and demodulation schemes and different communication standards in the same device. This is done by using reconfigurable and reprogrammable hardware and robust and powerful software. SDRs are easy to manufacture, are multi-functional, compact, power efficient and easy to upgrade.