Reduced complexity XOR trees for LDPC codes and BS-LFSR techniques to High-Speed memory applications

Abstract

Low-Density Parity Check (LDPC) Codes exhibit dominant role which deal with limitation of storage capacity. Hardware realization of Parity Check Codes is slow and consumes more power which makes it vulnerable for the light weight applications. Hence, to improve the throughput, area and power dissipation, parity check architectures must be constrained. This article proposes architecture of LDPC codes for high-speed memory applications with comparable XOR-gate tree-based VLSI design. The designed extension module includes Bit Swapping Linear Feedback Shift Register (BS-LFSR) technique that can illustrate and gauge expansion of faults in both the versions of faulty and fault-free. Furthermore, the power dissipation has been reduced by 8% and area by 83% with its extension module. This work has been designed using Vivado HLS and the hardware implementation of BS-LFSR has been verified on Zync 7000 series FPGA board for faulty and fault-free test patterns.