Hardware Platform Research Articles

TECHNOLOGY OF CREATION AND APPLICATION OF AN INTELLIGENT INFORMATION SYSTEM

This article provides formulated information about the design and implementation of the information system, the software product "Information system for personnel management of the department -(e-pedagog.uz)" was obtained, which allows automating the activities of the department of a higher educational institution. The software was fully tested in accordance with the program and test methodology. During testing, a number of errors regarding the correctness of calculations were identified and corrected. The check showed the operability of the system on all declared operating systems, as well as on various hardware platforms in the automation of the work of the department, namely the automation of the management processes of the department. The task of automation is the electronic recording of the individual plans of teachers of a higher educational institution is a key point in the analysis of the work of the entire higher educational institution as a whole. Automation of the process of fulfilling the teaching load by the teacher and filling out an individual plan: will allow you to calculate the theoretical and practical number of hours worked by the teacher automatically; will reduce the chance of error; control the publication activity of teachers of the department.

Hyperdimensional Brain-Inspired Learning for Phoneme Recognition With Large-Scale Inferior Colliculus Neural Activities.

Develop a novel and highly efficient framework that decodes Inferior Colliculus (IC) neural activities for phoneme recognition. We propose using Hyperdimensional Computing (HDC) to support an efficient phoneme recognition algorithm, in contrast to widely applied Deep Neural Networks (DNN). The high-dimensional representation and operations in HDC are rooted in human brain functionalities and naturally parallelizable, showing the potential for efficient neural activity analysis. Our proposed method includes a spatial and temporal-aware HDC encoder that effectively captures global and local patterns. As part of our framework, we deploy the lightweight HDC-based algorithm on a highly customizable and flexible hardware platform, i.e., Field Programmable Gate Arrays (FPGA), for optimal algorithm speedup. To evaluate our method, we record IC neural activities on gerbils while playing the sound of different phonemes. We compare our proposed method with multiple baseline machine learning algorithms in recognition quality and learning efficiency, across different hardware platforms. The results show that our method generally achieves better classification quality than the best-performing baseline. Compared to the Deep Residual Neural Network (i.e., ResNet), our method shows a speedup up to 74×, 67×, 210× on CPU, GPU, and FPGA respectively. We achieve up to 15% (10%) higher accuracy in consonant (vowel) classification than ResNet. By leveraging brain-inspired HDC for IC neural activity encoding and phoneme classification, we achieve orders of magnitude runtime speedup while improving accuracy in various challenging task settings. Decoding IC neural activities is an important step to enhance understanding about human auditory system. However, these responses from the central auditory system are noisy and contain high variance, demanding large-scale datasets and iterative model fine-tuning. The proposed HDC-based framework is more scalable and viable for future real-world deployment thanks to its fast training and overall better quality.

An efficient Grain-80 stream cipher with unrolling features to enhance the throughput on hardware platform

<span>The stream cipher is a fundamental component of symmetric cryptography and offers unique implementation speed and scalability advantages. Additionally, the complexity of the cipher algorithm deployment environment forces new, appropriate designs and challenges on the already-existing cipher algorithms. To increase throughput, an efficient Grain-80 stream cipher with unrolling features is designed in this manuscript. The Grain-80 cipher uses an 80-bit key, and a 64-bit initialization vector (IV) and contains two feedback shift registers (linear and non-linear) and an output function. The register balancing and unrolling features of the proposed Grian-80 cipher combine to increase throughput while requiring little additional hardware. Low latency, fast throughput, excellent efficiency, and reduced attack susceptibility are all features of the unrolling architecture. The proposed Grain-80 cipher utilizes <1% chip area and operates at 542.7 MHz on Artix-7 field programmable gate array (FPGA). The proposed Grain-80 cipher improves the operating frequency by 14.85% over conventional Grain-80 cipher. The Grain-80 cipher obtains the throughput of 4.35 Gbps and 8.69 Gbps for unrolling factors 8 and 16, respectively. Lastly, the proposed Grain-80 cipher is compared with existing Grain-80 ciphers with improved throughput and hardware efficiency.</span>

YOLOv5 Integrated With Recurrent Network for Object Tracking: Experimental Results From a Hardware Platform

YOLOv5 Integrated With Recurrent Network for Object Tracking: Experimental Results From a Hardware Platform

SMART CITY MANAGEMENT SYSTEM UTILIZAING MICRO-SERVICES AND IOT-BASED SYSTEMS

Urban governance is without a doubt a very complicated activity. The city doesn't just consist of people and buildings, there are transport and road infrastructure, critical infrastructure, medical facilities, road cover, industrial equipment and many more. Besides, the city council provides a wide range of services to the public. Among them healthcare, welfare, economic and finance supply, labor, real estate management and others. Information management systems and web services are employed for digital management, while various embedded management systems are used for equipment management and surveillance. Being very complex and multilayered system, Smart City Managment solutions offer a platform that encapsulates main services for both public and for technological aspects of urban governance. The results presented in this paper are based on a study of the existing software, hardware and middleware platforms for smart city use case. The main focus is middleware platform as it serves as medium that can connect existing software and hardware solutions. In the global context of Smart city management service system all major components are broken down in the format of microservices (on the level of large enterprise distributed service). Presented Managment software suit model had been broken down into multiple software architecture abstraction layers, from hardware to end-user application. As a result, the three stages smart city service implementation roadmap had been presented. Using the Middleware platform and Web-services models, the Smart City Managment services can be implemented in any given city in porotype stage for future evaluation and full version implementation.

Towards Full Stack Adaptivity in Permissioned Blockchains

This paper articulates our vision for a learning-based untrustworthy distributed database. We focus on permissioned blockchain systems as an emerging instance of untrustworthy distributed databases and argue that as novel smart contracts, modern hardware, and new cloud platforms arise, future-proof permissioned blockchain systems need to be designed with full-stack adaptivity in mind. At the application level, a future-proof system must adaptively learn the best-performing transaction processing paradigm and quickly adapt to new hardware and unanticipated workload changes on the fly. Likewise, the Byzantine consensus layer must dynamically adjust itself to the workloads, faulty conditions, and network configuration while maintaining compatibility with the transaction processing paradigm. At the infrastructure level, cloud providers must enable cross-layer adaptation, which identifies performance bottlenecks and possible attacks, and determines at runtime the degree of resource disaggregation that best meets application requirements. Within this vision of the future, our paper outlines several research challenges together with some preliminary approaches.

New digital low-level RF controls based on the Red Pitaya STEMlab for the TLS Linac system

The Linac system at Taiwan Light Source (TLS) has been in operation for almost a quarter of a century and requires upgrades to improve its reliability. To achieve this, some components of the control system have been replaced with new digital low-level RF control units that use emerging technologies. A new unit is based on the open-source hardware platform which is named “Red Pitaya STEMlab” and offers a compact size and low power consumption. The unit features DAC (Digital-to-Analog Converter) blocks for downloading arbitrary waveforms with external trigger play and ADC (Analog-to-Digital Converter) blocks for waveform acquisition, enabling the development of real-time diagnostic toolkits. The new low-level RF control interface has been fully integrated into the existing EPICS software framework for system integration. The new digital low-level RF control system supports I/Q (in-phase/quadra-ture-phase) data with online amplitude and phase set-tings, and a waveform digitizer for inspecting low-level RF signals from the klystron modulator. Specific graphical applications have been designed and integrated into the existing operation interfaces. The system has been successfully achieved during routine operations. This paper describes the details of these efforts.

A Memristive Spiking Neural Network Circuit for Bio-inspired Navigation Based on Spatial Cognitive Mechanisms.

Cognitive navigation, a high-level and crucial function for organisms' survival in nature, enables autonomous exploration and navigation within the environment. However, most existing works for bio-inspired navigation are implemented with non-neuromorphic computing. This work proposes a bio-inspired memristive spiking neural network (SNN) circuit for goal-oriented navigation, capable of online decision-making through reward-based learning. The circuit comprises three primary modules. The place cell module encodes the agent's spatial position in real-time through Poisson spiking; the action cell module determines the direction of subsequent movement; and the reward-based learning module provides a bio-inspired learning method adaptive to delayed and sparse rewards. To facilitate practical application, the entire SNN is quantized and deployed on a real memristive hardware platform, achieving about a 21× reduction in energy consumption compared to a typical digital acceleration system in the forward computing phase. This work offers an implementation idea of neuromorphic solution for robotic navigation application in low-power scenarios.

Research on electrical automation devices under embedded real-time operating system design

Abstract As the scale of the electrical system becomes more and more large and the structure becomes more and more complex, the performance of the electrical automation device is therefore required to be higher. This paper studies the electrical system automation device, and from the perspective of universality, designs and establishes the hardware platform of the electrical system automation device composed of six plug-ins, such as human-machine interface, auxiliary switch input, AC input, communication, power supply, and central processor. On this basis, μC/OS-II is adopted as the embedded real-time operating system of this paper to develop and design the software of the electrical system automation device. Then, the principle of the protection device for embedded system electrical automation is analyzed, and a microcomputer line protection device based on the full-circle Fuchs algorithm is proposed. The empirical analysis of the embedded system electrical automation device shows that the maximum system task response time is 145 μs and the minimum is 10 μs, which are all no more than 1 ms. When testing including the single board state, the keyboard, the alphabetical mode, the basic function, and the single board line module sending and receiving, the pass rate of all the testing items is more than 99%, which verifies that this paper is based on the embedded real-time operating system of the feasibility and effectiveness of the electrical automation device.

Low-Complexity P Class to M Class PMU Model for Distribution Systems

The paper presents a new PMU (Phasor Measurement Unit) signal processing model compliant with the IEC/IEEE 60255-118-1 standard. The disturbances are rejected by a cascade digital prefilter made of sections, each with one nominal cycle long rectangular impulse response. The frequency is next estimated by the discrete-time frequency-gain transducer (DTFGT). A single section prefilter with the DTFGT is a 1.5 nominal cycle long P class compliant PMU. M class compliance requires 13 sections prefilter what, along with the DTFGT, gives a 13.4 cycle long PMU. By the elongation of the prefilter cascade, with one cycle increment, the transition from the 1.5 cycle P class to the 13.4 cycle M class PMU is obtained. Each cascade section filter is implemented recursively with only two additions and one multiplication independently of the assumed sampling frequency. The phasor is precisely estimated thanks to the proposed correction of amplitude attenuation and phase shift caused by the prefilter. The main advantages of the proposed PMU model are: full compliance with the standard, low computational complexity, superior rejection of harmonics, and possibility of phasor quality assessment based on different length PMU estimations. The proposed PMU model is primary meant for the distribution systems because of high immunity to disturbances and low computational complexity that makes it suitable for implementation in a low-cost hardware platform or as a software module in a virtual instrumentation and large-scale deployment.

GRASPA-fying the Panda: Easily Deployable, Fully Reproducible Benchmarking of Grasp Planning Algorithms

Although robotic grasp planning has been extensively studied in the literature, comparing the performance of different approaches still proves challenging due to the lack of standardization in hardware setup and benchmarking protocols. This work addresses the issue with a threefold contribution. First, it provides a standardized hardware platform and a software framework integrating a benchmarking protocol for grasp planning algorithms (GRASPA). Second, it uses such a framework to benchmark three state-of-the-art algorithms in a reproducible way. Third, it employs the framework to investigate the effect of camera pose variance in visual-based grasp planning. We show how the proposed benchmarking setup can be used to provide insight into the results, not only to compare different vision-based grasp planners but also to evaluate different parameter configurations within the same grasp planner, for instance, camera viewpoint with respect to the scene. To ease the reproducibility of our results and usability of the platform, we provide extensive information for replicating the experimental setup and installing our software in the supplementary material (available at <ext-link ext-link-type="uri" xlink:href="https://doi.org/10.1109/MRA.2023.3256272" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">https://doi.org/10.1109/MRA.2023.3256272</ext-link> ). All the software used in this article is freely available online in the form of Docker images.

Towards High-Performance AI4NP Applications on Modern GPU Platforms

The evolution of modern heterogeneous accelerators, such as GPUs, has significantly advanced the landscape of artificial intelligence (AI). There is a notable surge to adopt AI within the nuclear physics domain (AI4NP). While most AI4NP studies focus on feasibility analysis, our attention is directed towards evaluating their performance on contemporary GPUs that integrate tensor cores. We first benchmark the throughput of hyperparameterized multi-layer perceptron (MLP) models. We then examine the performance of an AI4NP application: Hydra. We assess the performance gain and accuracy loss caused by the tensor cores for low-precision floating-point operations. Our experiments encompass the PyTorch and TensorFlow Keras frameworks on NVIDIA’s T4 and A100 GPUs. We explore the behavior of different GPU hardware platforms and AI software tools. This study can be a valuable resource for guiding the performance optimization of larger-scale deployments of AI4NP applications.

A High-Performance Pixel-Level Fully Pipelined Hardware Accelerator for Neural Networks.

The design of convolutional neural network (CNN) hardware accelerators based on a single computing engine (CE) architecture or multi-CE architecture has received widespread attention in recent years. Although this kind of hardware accelerator has advantages in hardware platform deployment flexibility and development cycle, it is still limited in resource utilization and data throughput. When processing large feature maps, the speed can usually only reach 10 frames/s, which does not meet the requirements of application scenarios, such as autonomous driving and radar detection. To solve the above problems, this article proposes a full pipeline hardware accelerator design based on pixel. By pixel-by-pixel strategy, the concept of the layer is downplayed, and the generation method of each pixel of the output feature map (Ofmap) can be optimized. To pipeline the entire computing system, we expand each layer of the neural network into hardware, eliminating the buffers between layers and maximizing the effect of complete connectivity across the entire network. This approach has yielded excellent performance. Besides that, as the pixel data stream is a fundamental paradigm in image processing, our fully pipelined hardware accelerator is universal for various CNNs (MobileNetV1, MobileNetV2 and FashionNet) in computer vision. As an example, the accelerator for MobileNetV1 achieves a speed of 4205.50 frames/s and a throughput of 4787.15 GOP/s at 211 MHz, with an output latency of 0.60 ms per image. This extremely shorts processing time and opens the door for AI's application in high-speed scenarios.

Acoustic Spectral Analysis for Emergency Vehicle Detection: Symbolic and CNN Approaches

During emergencies, ambulances on city streets face delays due to traffic obstacles. This paper addresses two efficient emergency vehicle detection (EVD) methods for restricted hardware implementation considering noisy conditions: a symbolic processing-based algorithm and a convolutional neural network (CNN) model, both of which utilize Mel spectrogram representations of Hi-Lo siren audio records. The symbolic method employs regular expressions and acceptance criteria to process text-pattern features extracted from spectrograms, offering a self-explanatory, easily tunable, and resource-efficient solution suitable for lowcost hardware platforms. On the other hand, the CNN model directly processes spectrogram representations, leveraging spatial correlation for classification with a streamlined architecture consisting of very few layers. The experimental results demonstrate that both approaches achieve high accuracy (97-98%) in classifying Hi-Lo sirens, with the CNN model exhibiting slightly better performance. Challenges such as signal noise and harmonics are addressed through iterative algorithms and signal reconstruction considerations. Future directions include identifying additional siren effects and conducting performance measurements on constrained hardware devices. Overall, this study presents viable EVD solutions suitable for real-time implementation and underscores the importance of adaptable and explainable AI methods in enhancing road safety.

Deep Learning-Based Traffic Light Detection in a Custom Embedded Hardware Platform for ADAS Applications

Deep Learning-Based Traffic Light Detection in a Custom Embedded Hardware Platform for ADAS Applications

DESIGN AND DEVELOPMENT OF AI CLOUD-BASED VIDEO RECORDING SYSTEM FOR ATHLETE MOVEMENTS

This paper presents the design and development of an AI cloud-based video recording system for athlete move- ment analysis. The proposed system utilizes the Wemos D1 Mini microcontroller as the core hardware platform and a GoPro cam- era for high-quality video capture. By leveraging the capabilities of these components, the system enables real-time video re- cording of athlete movements, facilitating detailed performance analysis and feedback. Furthermore, the system seamlessly inte- grates with Amazon Web Services (AWS) IoT Core, enabling efficient data transmission and storage in the cloud. Through re- search and development, both the hardware and software components of the system were designed and implemented, ensuring robust performance and scalability. Experiments demonstrate the efficacy of the proposed solution in capturing high-fidelity video footage of athlete movements and securely transmitting it to the cloud for further analysis. This research lays the foundation for advanced athlete monitoring systems, offering valuable insights for coaches, trainers, and sports scientists to enhance training regimens and optimize performance.

Software-Defined Analog Processing Based on IEC 61850 Implemented in an Edge Hardware Platform to be Used in Digital Substations

Software-Defined Analog Processing Based on IEC 61850 Implemented in an Edge Hardware Platform to be Used in Digital Substations

BENCHMARKING AND IMPLEMENTING DEEP LEARNING ALGORITHMS ON FIELD PROGRAMMABLE GATE ARRAYS AND APLLICATION SPECIFIC INTEGRAL CIRCUIT PLATFORMS

Issues on the enhancement of Artificial Intelligence (AI) performance using Field-Programmable Gate Arrays (FPGA) and Application-Specific Integrated Circuits (ASIC) are studied. It focuses on benchmarking and implementing deep learning algorithms, crucial components of modern AI, on these advanced hardware platforms. The study begins with an explanation of the significance of deep learning in AI and the growing need for efficient computing platforms like FPGA and ASIC. These platforms are known for their high-speed processing capabilities and low power consumption, making them ideal for AI applications. The research then delves into a detailed analysis of how deep learning algorithms can be optimized and executed on FPGA and ASIC platforms. It highlights the methods used to benchmark the performance of these algorithms on the mentioned hardware, providing a clear comparison with traditional computing systems. The paper also discusses the challenges and solutions in integrating deep learning algorithms into these specialized hardware environments. Further, the advantages of using FPGA and ASIC for AI tasks, including improved processing speed, reduced energy consumption, and enhanced ability to handle complex AI computations are studied.

MCMC: Multi-Constrained Model Compression via One-Stage Envelope Reinforcement Learning.

Model compression methods are being developed to bridge the gap between the massive scale of neural networks and the limited hardware resources on edge devices. Since most real-world applications deployed on resource-limited hardware platforms typically have multiple hardware constraints simultaneously, most existing model compression approaches that only consider optimizing one single hardware objective are ineffective. In this article, we propose an automated pruning method called multi-constrained model compression (MCMC) that allows for the optimization of multiple hardware targets, such as latency, floating point operations (FLOPs), and memory usage, while minimizing the impact on accuracy. Specifically, we propose an improved multi-objective reinforcement learning (MORL) algorithm, the one-stage envelope deep deterministic policy gradient (DDPG) algorithm, to determine the pruning strategy for neural networks. Our improved one-stage envelope DDPG algorithm reduces exploration time and offers greater flexibility in adjusting target priorities, enhancing its suitability for pruning tasks. For instance, on the visual geometry group (VGG)-16 network, our method achieved an 80% reduction in FLOPs, a 2.31× reduction in memory usage, and a 1.92× acceleration, with an accuracy improvement of 0.09% compared with the baseline. For larger datasets, such as ImageNet, we reduced FLOPs by 50% for MobileNet-V1, resulting in a 4.7× faster speed and 1.48× memory compression, while maintaining the same accuracy. When applied to edge devices, such as JETSON XAVIER NX, our method resulted in a 71% reduction in FLOPs for MobileNet-V1, leading to a 1.63× faster speed, 1.64× memory compression, and an accuracy improvement.

A Blueprint for a Contemporary Storage Element, building a new WLCG storage system with widely available hardware and software components: Ceph, XRootD, and Prometheus

When a new long-term storage facility was needed at the Lancaster WLCG Tier-2 Site, an architecture was chosen involving CephFS as a failure-tolerant back-end volume, and load-balanced XRootD as an endpoint exposing the volume via the HTTPS/DAVS protocols increasingly favoured by the WLCG and other users. This allows operations to continue in the face of disc/node failures with minimal management, and enables good utilization of network connectivity for remote access. We deployed a Prometheus/Loki/Grafana monitoring/alerting stack for timely detection and resolution of failures in such a production environment. Some custom scripts were required to adapt the off-the-shelf functional components with monitoring. With such a monitoring system in place, failures such as disc defects, data corruption and resource exhaustion in long-running processes can be anticipated, and their management planned. We describe the hardware platform and our requirements on it, and detail the software architecture from initial design, through adaptations to face challenges encountered during production, to present condition. Developments and contributions to related projects that help to fully exploit our design decisions are described. We include performance metrics of the system, the lessons learned during production, and our future plans.