Hardware Platform Research Articles

Theoretical Validation and Hardware Implementation of Dynamic Adaptive Scheduling for Heterogeneous Systems on Chip

Domain-specific systems on chip (DSSoCs) aim to narrow the gap between general-purpose processors and application-specific designs. CPU clusters enable programmability, whereas hardware accelerators tailored to the target domain minimize task execution times and power consumption. Traditional operating system (OS) schedulers can diminish the potential of DSSoCs, as their execution times can be orders of magnitude larger than the task execution time. To address this problem, we propose a dynamic adaptive scheduling (DAS) framework that combines the advantages of a fast, low-overhead scheduler and a sophisticated, high-performance scheduler with a larger overhead. We present a novel runtime classifier that chooses the better scheduler type as a function of the system workload, leading to improved system performance and energy-delay product (EDP). Experiments with five real-world streaming applications indicate that DAS consistently outperforms fast, low-overhead, and slow, sophisticated schedulers. DAS achieves a 1.29× speedup and a 45% lower EDP than the sophisticated scheduler under low data rates and a 1.28× speedup and a 37% lower EDP than the fast scheduler when the workload complexity increases. Furthermore, we demonstrate that the superior performance of the DAS framework also applies to hardware platforms, with up to a 48% and 52% reduction in the execution time and EDP, respectively.

Instrumentation for Verification of Shunt Active Power Filter Algorithms.

This article presents a comprehensive system for testing and verifying shunt active power filter control methods. The aim of this experimental platform is to provide tools to a user to objectively compare the individual control methods. The functionality of the system was verified on a hardware platform using least mean squares and recursive least squares algorithms. In the experiments, an average relative suppression of the total harmonic distortion of 22% was achieved. This article describes the principle of the shunt active power filter, the used experimental platform of the controlled current injection source, its control system based on virtual instrumentation and control software and ends with experimental verification. The discussion of the paper outlines the extension of the experimental platform with the cRIO RTOS control system to reduce the latency of reference current generation and further planned research including motivation.

A Secure Key Expansion Algorithm for Present

The efficiency of a cryptographic algorithm in terms of security depends on the resistance against cryptanalytic attacks. Besides the complexity of the encryption algorithm, the key plays an essential role in the security against cryptanalytic attacks. The strength and complexity of the encryption algorithm do not suffice and serve the fundamental purpose of security if the key is compromised at any stage. So, apart from the cryptanalytically robust encryption algorithm, a strong key schedule is also essential to thwart possible attacks against a particular algorithm. PRESENT, a lightweight encryption technique with a simple design, is resistant to linear and differential attacks but has a weak key schedule and is susceptible to cryptanalytic attacks. This paper proposes an efficient key scheduling algorithm for PRESENT lightweight encryption technique resistant against cryptanalytic attacks. Statistical tests examine the proposed key schedule’s cryptographic strength on the properties of subkeys produced in the key generation mechanism. The tests prove the efficiency of the proposed key schedule in terms of cryptanalytic attacks. Implementation and comparison of the efficacy of the proposed key schedule in terms of security and implementation costs are illustrated with the PRESENT-80 key schedule and the PRESENT-128 key schedule. The key scheduling algorithm is implemented on the ARM Cortex M3-based NXP LPC 1857 and 1768 hardware development platforms. The results indicate the efficiency of the proposed algorithm in terms of security, performance, and power consumption across the two hardware platforms.

A lightweight dense crowd density estimation network for efficient compression models

Crowd density estimation is a task of intelligent applications, and its operation efficiency is very important. However, to obtain a better density estimation performance, most of the existing works often design larger and more complex network structures, which will result in them occupying considerable memory, time and other resources at runtime, and require the support of high-performance hardware platforms, which are difficult to apply in practice. In this paper, to overcome the above problems, we propose a lightweight dense crowd estimation method based on channel attention multi-scale feature fusion. Specifically, in the process of feature extraction, an efficient and lightweight convolution module (L-weight) is designed to extract crowd features in stages, which reduces the amount of network parameters and computing costs, and we capture multi-scale crowd information through the feature extraction network of pyramid structure, which solves the problem of uneven crowd scale in video images. In the process of feature fusion, a channel attention fusion module is designed, which weights and fuses the feature information of different scales, effectively fuses multi-scale information and suppresses useless information. In addition, we design a new loss function, which enhances the sensitivity of the crowd through the pixel space loss (L2), counting loss (LC) and structural similarity loss (LS), to ensure the counting accuracy. Extensive experiments on four mainstream datasets demonstrate that compared with other state-of-the-art methods, our method achieves an optimal trade-off between counting performance and running speed, and is suitable for low-performance computing platforms such as embedded.

An ensembled method for air quality monitoring and control using machine learning

Air quality monitoring is a significant job in our everyday life and affects the vitality of a human. It paves a better way of understanding the sources, effects and levels of pollutants in the air inhaled by the population of the region. This concept helps us in improving and developing pollution control measures to diminish the effect of air contamination. Air Quality Index (AQI) helps in understanding the level of pollution. This study briefs various state of art methods such as SVM, RF,ANN, RNN and FL in predicting air quality using machine learning. The results shows prominent outcomes which can be deployed in various cost effective hardware platforms for household and commercial purposes. The proposed model used eight parameters like NO2CO, O3, PM2.5, PM10, SO2, TEMP, PRES, DEWP, RAIN,WD, WSPM of Beijing dataset in order to predict AQI and it is tested with regional dataset. The Proposed model works based on process monitoring model. The efficient and flexible way to solve environmental issues is to combine machine learning algorithm with air quality prediction.

FPGA-based Deep Learning Inference Accelerators: Where Are We Standing?

Recently, artificial intelligence applications have become part of almost all emerging technologies around us. Neural networks, in particular, have shown significant advantages and have been widely adopted over other approaches in machine learning. In this context, high processing power is deemed a fundamental challenge and a persistent requirement. Recent solutions facing such a challenge deploy hardware platforms to provide high computing performance for neural networks and deep learning algorithms. This direction is also rapidly taking over the market. Here, FPGAs occupy the middle ground regarding flexibility, reconfigurability, and efficiency compared to general-purpose CPUs, GPUs, on one side, and manufactured ASICs on the other. FPGA-based accelerators exploit the features of FPGAs to increase the computing performance for specific algorithms and algorithm features. Filling a gap, we provide holistic benchmarking criteria and optimization techniques that work across several classes of deep learning implementations. This article summarizes the current state of deep learning hardware acceleration: More than 120 FPGA-based neural network accelerator designs are presented and evaluated based on a matrix of performance and acceleration criteria, and corresponding optimization techniques are presented and discussed. In addition, the evaluation criteria and optimization techniques are demonstrated by benchmarking ResNet-2 and LSTM-based accelerators.

Scientific Computing with Diffractive Optical Neural Networks

Diffractive optical neural networks (DONNs) are emerging as high‐throughput and energy‐efficient hardware platforms to perform all‐optical machine learning (ML) in machine vision systems. However, the current demonstrated applications of DONNs are largely image classification tasks, which undermine the prospect of developing and utilizing such hardware for other ML applications. Herein, the deployment of an all‐optical reconfigurable DONNs system for scientific computing is demonstrated numerically and experimentally, including guiding two‐dimensional quantum material synthesis, predicting the properties of two‐dimensional quantum materials and small molecular cancer drugs, predicting the device response of nanopatterned integrated photonic power splitters, and the dynamic stabilization of an inverted pendulum with reinforcement learning. Despite a large variety of input data structures, a universal feature engineering approach is developed to convert categorical input features to images that can be processed in the DONNs system. The results open up new opportunities for employing DONNs systems for a broad range of ML applications.

Design and research of music teaching system based on virtual reality system in the context of education informatization.

Virtual Reality (VR) technology uses computers to simulate the real world comprehensively. VR has been widely used in college teaching and has a huge application prospect. To better apply computer-aided instruction technology in music teaching, a music teaching system based on VR technology is proposed. First, a virtual piano is developed using the HTC Vive kit and the Leap Motion sensor fixed on the helmet as the hardware platform, and using Unity3D, related SteamVR plug-ins, and Leap Motion plug-ins as software platforms. Then, a gesture recognition algorithm is proposed and implemented. Specifically, the Dual Channel Convolutional Neural Network (DCCNN) is adopted to collect the user's gesture command data. The dual-size convolution kernel is applied to extract the feature information in the image and the gesture command in the video, and then the DCCNN recognizes it. After the spatial and temporal information is extracted, Red-Green-Blue (RGB) color pattern images and optical flow images are input into the DCCNN. The prediction results are merged to obtain the final recognition result. The experimental results reveal that the recognition accuracy of DCCNN for the Curwen gesture is as high as 96%, and the recognition accuracy varies with different convolution kernels. By comparison, it is found that the recognition effect of DCCNN is affected by the size of the convolution kernel. Combining convolution kernels of size 5×5 and 7×7 can improve the recognition accuracy to 98%. The research results of this study can be used for music teaching piano and other VR products, with extensive popularization and application value.

Advancements in spiking neural network communication and synchronization techniques for event-driven neuromorphic systems

Neuromorphic event-driven systems emulate the computational mechanisms of the brain through the utilization of spiking neural networks (SNN). Neuromorphic systems serve two primary application domains: simulating neural information processing in neuroscience and acting as accelerators for cognitive computing in engineering applications. A distinguishing characteristic of neuromorphic systems is their asynchronous or event-driven nature, but even event-driven systems require some synchronous time management of the neuron populations to guarantee sufficient time for the proper delivery of spiking messages. In this study, we assess three distinct algorithms proposed for adding a synchronization capability to asynchronous event-driven compute systems. We run these algorithms on POETS (Partially Ordered Event-Triggered Systems), a custom-built FPGA-based hardware platform, as a neuromorphic architecture. This study presents the simulation speed of SNNs of various sizes. We explore essential aspects of event-driven neuromorphic system design that contribute to efficient computation and communication. These aspects include varying degrees of connectivity, routing methods, mapping techniques onto hardware components, and firing rates. The hardware mapping and simulation of up to eight million neurons, where each neuron is connected to up to one thousand other neurons, are presented in this work using 3072 reconfigurable processing cores, each of which has 16 hardware threads. Using the best synchronization and communication methods, our architecture design demonstrates 20-fold and 16-fold speedups over the Brian simulator and one 48-chip SpiNNaker node, respectively. We conclude with a brief comparison between our platform and existing large-scale neuromorphic systems in terms of synchronization, routing, and communication methods, to guide the development of future event-driven neuromorphic systems.

Collision Avoidance of Autonomous Driving at Low Speed in the Near Field of Vehicle

This paper aims to propose a new idea for realizing low-power-consumption, real-time, microcontroller-based, redundant embedded collision avoidance systems in autonomous driving applications. When operating a fully automated vehicle, the vehicle generates a driving trajectory based on the global route to the destination. The car must follow the generated driving path. It is essential to ensure the safety of this path by checking that it is collision-free. The goal of our low-level embedded collision avoidance system is to guarantee the safety of the path. After defining the driving path area associated with the generating path and the safe monitoring distance, the system can monitor the vehicle's defined Keep-Out-Area (KOA) by using 3D Light Detection and Ranging (LiDAR) sensor. Considering the relatively limited computing power of the microcontroller, the KOA is calculated offline and stored in a look-up table (LUT). This paper also introduces an experimental hardware platform based on the proposed system concept. This platform can facilitate the testing of various collision avoidance algorithms. Moreover, we also identify the challenges, such as false positives and deviation from the actual driving path.

Метод створення і впровадження FPGA проєктів стійких до змін вимог і середовищ розроблення для хмарних інфраструктур

The subject of study in this article is the modern technologies of programmable logic devices, the history of product changes of leading manufacturers, including development environments, and project optimization processes. The goal is to improve modern methods, technologies, and software tools for the development and integration of FPGA-as-a-Service in the form of services in cloud infrastructures, data centers, and on-board high-performance systems, with taking into account the ever-changing conditions and requirements, and the constraints of platforms. Task: to analyze the history of product changes of the leading vendors and manufacturers of programmable logic devices; analyze the dynamics of changes in the functionality of project development environments for FPGA-based systems, with taking into account the existing requirements and restrictions from vendors of software and hardware platforms and components; perform a comparative analysis of modern development boards and accelerator cards for the prototyping and testing of projects based on the chips of programmable logic; analyze the use of an existing services and solutions based on FPGA technologies as part of cloud services from modern cloud providers; propose practical steps for the development of systems based on FPGA resistant to project requirements change; propose the sequence for the development and optimization of high-performance systems with their implementation based on FPGA; and to provide practical example of the use of the proposed method. According to the tasks, the following results were obtained. The history of changes in the leading companies of programmable logic manufacturers, as well as changes in versions of the development environments and the products of one of the largest companies, is analyzed. The use of existing FPGA-based solutions as part of cloud services is analyzed in detail. Two sequences for optimizing projects and increasing their productivity with reducing of the prototyping efforts during their creation and porting to new versions of software and hardware platforms are provided. Based on the results of the research, a prototype was developed and tested, which allowed the application of the proposed method in practice for adapting and porting the FPGA as a service project during the transfer to another version of the accelerator card. Conclusions. The main contribution and scientific novelty of the obtained results is that an experimental study of the paradigm of runtime reprogramming of programmable logic was performed, which made it possible to formulate the elements of a new method of creation projects as a service for cloud infrastructures, data centers, and artificial intelligence systems. A set of practical steps for the development of systems that are tolerant to changes in conditions and requirements is proposed. The application of the proposed method allows to avoid costs of project support in the case of changes in requirements.

A multi-microcontroller-based hardware for deploying Tiny machine learning model

<span lang="EN-US">The tiny machine learning (TinyML) has been considered to applied on the edge devices where the resource-constrained micro-controller units (MCUs) were used. Finding a good platform to deploy the TinyML effectively is very crucial. The paper aims to propose a multiple micro-controller hardware platform for productively running the TinyML model. The proposed hardware consists of two dual-core MCUs. The first MCU is utilized for acquiring and processing input data, while the second is responsible for executing the trained TinyML network. Two MCUs communicate to each other using the universal asynchronous receiver-transmitter (UART) protocol. The multi-tasking programming technique is mainly applied on the first MCU to optimize the pre-processing new data. A three-phase motors faults classification TinyML model was deployed on the proposed system to evaluate the effectiveness. The experimental results prove that our proposed hardware platform was improved 34.8% the total inference time including pre-processing data of the proposed TinyML model in comparing with single micro-controller hardware platform.</span>

Secured authentication of radio-frequency identification system using PRESENT block cipher

<span lang="EN-US">The internet of things (IoT) is an emerging and robust technology to interconnect billions of objects or devices via the internet to communicate smartly. The radio frequency identification (RFID) system plays a significant role in IoT systems, providing most features like mutual establishment, key establishment, and data confidentiality. This manuscript designed secure authentication of IoT-based RFID systems using the light-weight PRESENT algorithm on the hardware platform. The PRESENT-256 block cipher is considered in this work, and it supports 64-bit data with a 256-key length. The PRESENT-80/128 cipher is also designed along with PRESENT-256 at electronic codebook (ECB) mode for Secured mutual authentication between RFID tag and reader for IoT applications. The secured authentication is established in two stages: Tag recognition from reader, mutual authentication between tag and reader using PRESENT-80/128/256 cipher modules. The complete secured authentication of IoT-based RFID system simulation results is verified using the chip-scope tool with field-programmable gate array (FPGA) results. The comparative results for PRESENT block cipher with existing PRESENT ciphers and other light-weight algorithms are analyzed with resource improvements. The proposed secured authentication work is compared with similar RFID-mutual authentication (MA) approaches with better chip area and frequency improvements.</span>

An efficient asynchronous spatial division multiplexing router for network-on-chip on the hardware platform

The quasi-delay-insensitive (QDI) based asynchronous network-on-chip (ANoC) has several advantages over clock-based synchronous network-on-chips (NoCs). The asynchronous router uses a virtual channel (VC) as a primary flow-control mechanism however, the spatial division multiplexing (SDM) based mechanism performs better over input traffics over VC. This manuscript uses an asynchronous spatial division multiplexing (ASDM) based router for NoC architecture on a field-programmable gate array (FPGA) platform. The ASDM router is configurable to different bandwidths and VCs. The ASDM router mainly contains input-output (I/O) buffers, a switching allocator, and a crossbar unit. The 4-phase 1-of-4 dual-rail protocol is used to construct the I/O buffers. The performance of the ASDM router is analyzed in terms of lower urinary tract symptoms (LUTs) (chip area), delay, latency, and throughput parameters. The work is implemented using Verilog-HDL with Xilinx ISE 14.7 on artix-7 FPGA. The ASDM router achieves % chip area and obtains 0.8 ns of latency with a throughput of 800 Mfps. The proposed router is compared with existing asynchronous approaches with improved latency and throughput metrics.

A Novel 4D Conservative Chaotic System with Hidden Extreme Multistability, Special Multitransient Behaviors, and Offset Boosting Behaviors

In this paper, we propose a novel 4D conservative chaotic system with a variety of interesting dynamic behaviors. By analyzing the divergence, Lyapunov exponent, equilibrium point and K-Y dimension of the proposed system, it is found that the system has hidden attractors and conservative characteristics. When the control parameters and initial values of the 4D conservative chaotic system are set to different values, the system shows hidden extreme multistability and offset boosting behaviors. In addition, in the case of fixed control parameters, when different initial values are selected, the system exhibits a variety of special transient transition behaviors, including quasi-periodic to periodic, quasi-periodic to hyperchaotic state. Subsequently, compared with existing systems, the complexity analysis of the chaotic sequence shows that the proposed system has a significant improvement in terms of sequence complexity. Finally, the system is implemented through a DSP hardware platform, preparing for subsequent engineering applications.

Ship-Mounted Cranes Hoisting Underwater Payloads: Transportation Control With Guaranteed Constraints on Overshoots and Swing

In recent years, with the rapid development of marine engineering, ship-mounted crane control for transporting payloads in the water has attracted more attention. Compared with the case of transporting payloads above water, ship-mounted cranes with underwater payloads are more difficult to control. On the one hand, the underwater payload is directly affected by the hydrodynamic force, and the dynamics of ship-mounted cranes is much more complex, nonlinear, and coupled; on the other hand, the unactuated underwater payload swing is quite sensitive to external disturbances; thus, the harsh marine environment will bring great challenges to the anti-swing control of underwater payloads. To address the above issues, this article puts forward a coupling characteristic indicator(CCI)-based nonlinear control method to realize accurate positioning and swing suppression for ship-mounted cranes hoisting payloads in the water, which not only simultaneously suppresses actuated boom overshoots and constrains <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">unactuated</i> payload swing, but also indicates whether the coupling terms are beneficial or harmful to make full use of them to improve transient control performance. Rigorous theoretical derivation proves the closed-loop stability. To the best of our knowledge, this is the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">first</i> solution to handle state constraints and utilizing the coupling characteristics of ship-mounted cranes for transferring payloads in the water. Finally, the proposed controller is applied to a self-made hardware platform, and the experimental results show that the designed method achieves satisfactory control performance.

Everest: GPU-Accelerated System for Mining Temporal Motifs

Temporal motif mining is the task of finding the occurrences of subgraph patterns within a large input temporal graph that obey the specified structural and temporal constraints. Despite its utility in several critical application domains that demand high performance ( e.g. , detecting fraud in financial transaction graphs), the performance of existing software is limited on commercial hardware platforms, in that it runs for tens of hours. This paper presents Everest---a system that efficiently maps the workload of mining (supports both enumeration and counting) temporal motifs to the highly parallel GPU architecture. In particular, using an input temporal graph and a more expressive user-defined temporal motif query definition compared to prior works, Everest generates an execution plan and runtime primitives that optimize the workload execution by exploiting the high compute throughput of a GPU. Everest generates motif-specific mining code to reduce long-latency memory accesses and frequent thread divergence operations. Everest incorporates novel low-cost runtime mechanisms to enable load balancing to improve GPU hardware utilization. To support large graphs that do not fit on GPU memory, Everest also supports multi-GPU execution by intelligently partitioning the edge list that prevents inter-GPU communication. Everest hides the implementation complexity of presented optimizations away from the targeted system user for better usability. Our evaluation shows that, using proposed optimizations, Everest improves the performance of a baseline GPU implementation by 19X, on average.

PROJECT METHOD IN STEM EDUCATION USING ARDUINO SOFTWARE AND HARDWARE PLATFORM

Formulation of the problem. One of the promising methods of training in STEM education is the method of projects. The projected method in STEM education determines the relevance and research nature of the topic of the project, ensuring the interconnection of theoretical knowledge with practice, practical implementation of the results of the project. The project, as a means of implementing STEM education, allows you to integrate knowledge from different subject industries when solving real tasks, the creation of existing layouts, which causes their practical use. Materials and methods. Methods of analysis and systematization of scientific and pedagogical literature were used; generalization of the results of domestic and foreign experience in the use of a prose method in the STEM education using the ARDUino software and hardware platform. The experimental method of creating an active physiotherapy laser device for treatment of the runny nose is presented. A software modeling is used to simulate a device with the design of the Arduino Uno board. Results. The example of the implementation of the STEM project "Development of a physiotherapeutic laser device for the treatment of runny nose" demonstrates how it is possible to integrate many different-level, didactic, and research tasks. A generalized description of the main structural elements of the Arduino Uno board is given. A typical algorithm for familiarizing yourself with the operation of the Arduino board is formulated. The main sections of the physics course are indicated, the knowledge of which is fundamental for implementing the project. It is shown how using a bit matrix of laser states allows the creation of cyclic irradiation modes that periodically change each other. An example of a code processing a bit matrix of laser states is provided. The sketch controls the modes of the semiconductor laser, displays the exposure time on the liquid crystal display, and emits a sound signal at the end of the exposure time set by the potentiometer. A fragment of the simulation modeling of a physiotherapy device in the Tinkercad Circuits environment is presented. Conclusions. The practical experience of using the project method in STEM education has shown that it allows students to investigate a real problem actively, apply the acquired knowledge in practice, and develop cooperation, communication, and critical thinking skills. Implementation of the project contributes to the combination of various activities, such as cognitive, creative, practical, and research, as well as the development of thinking skills, motivation, and responsibility for one's actions. Implementing the project method makes it possible to provide high-quality training for specialists in natural sciences who can effectively apply their knowledge and skills in practical situations and contribute to the further development of STEM fields in Ukraine.

Supporting logical execution time in multi-core POSIX systems

Safety-critical automotive applications require predictable and deterministic execution to not miss the timing requirements. Logical Execution Time (LET) is a paradigm already established in the automotive industry to improve the predictability and correctness of time-critical applications. Despite LET being already part of the AUTOSAR Classic standard, no prior work has addressed the design of this model on POSIX-based operating systems, which will be the base of next-generation automotive Electronic Control Units (ECUs). This paper proposes and discusses possible LET design approaches for these novel systems. Different implementations are then evaluated and compared through the WATERS Challenge automotive application running on a multi-core heterogeneous hardware platform.

Feasibility of Nurse-led Development of Custom Virtual Reality Experiences for Health Care Interventions.

The immersive and interactive nature of virtual reality (VR) renders it a potential pedagogical approach for nursing education. A bottleneck for exploiting VR advantages has been the complexity of creating new experiences; however, recent advances with VR hardware and software enable novice users to create compelling experiences. A case study describes an undergraduate nursing student with minimal technical skills using off-the-shelf VR software to create a pain management VR experience. Using off-the-shelf hardware and software platforms eliminates the need to work with computer code. The team created a virtual environment and the objects in it through easy manipulation with click-and-drag techniques and by toggling simple settings. The insights gained from this case suggest nurse educators can create simple yet powerful VR experiences themselves, which can greatly enhance existing tools for nursing education. [J Nurs Educ. 2024;63(4):261-264.].