Hardware Optimization Research Articles

Finding the Top-K Heavy Hitters in Data Streams: A Reconfigurable Accelerator Based on an FPGA-Optimized Algorithm

This paper presents a novel approach for accelerating the top-k heavy hitters query in data streams using Field Programmable Gate Arrays (FPGAs). Current hardware acceleration approaches rely on the direct and strict mapping of software algorithms into hardware, limiting their performance and practicality due to the lack of hardware optimizations at an algorithmic level. The presented approach optimizes a well-known software algorithm by carefully relaxing some of its requirements to allow for the design of a practical and scalable hardware accelerator that outperforms current state-of-the-art accelerators while maintaining near-perfect accuracy. This paper details the design and implementation of an optimized FPGA accelerator specifically tailored for computing the top-k heavy hitters query in data streams. The presented accelerator is entirely specified at the C language level and is easily reproducible with High-Level Synthesis (HLS) tools. Implementation on Intel Arria 10 and Stratix 10 FPGAs using Intel HLS compiler showed promising results—outperforming prior state-of-the-art accelerators in terms of throughput and features.

DETECTING LOW BACK PHYSIOTHERAPY EXERCISES AND POSTURES WITH INERTIAL SENSORS AND MACHINE LEARNING

Physiotherapy is a critical element in successful conservative management of low back pain (LBP). The aim of this study was to develop and evaluate a system with wearable inertial sensors to objectively detect sitting postures and performance of unsupervised exercises containing movement in multiple planes (flexion, extension, rotation).A set of 8 inertial sensors were placed on 19 healthy adult subjects. Data was acquired as they performed 7 McKenzie low-back exercises and 3 sitting posture positions. This data was used to train two models (Random Forest (RF) and XGBoost (XGB)) using engineered time series features. In addition, a convolutional neural network (CNN) was trained directly on the time series data. A feature importance analysis was performed to identify sensor locations and channels that contributed most to the models. Finally, a subset of sensor locations and channels was included in a hyperparameter grid search to identify the optimal sensor configuration and the best performing algorithm(s) for exercise classification. Models were evaluated using F1-score in a 10-fold cross validation approach.The optimal hardware configuration was identified as a 3-sensor setup using lower back, left thigh, and right ankle sensors with acceleration, gyroscope, and magnetometer channels. The XBG model achieved the highest exercise (F1=0.94±0.03) and posture (F1=0.90±0.11) classification scores. The CNN achieved similar results with the same sensor locations, using only the accelerometer and gyroscope channels for exercise classification (F1=0.94±0.02) and the accelerometer channel alone for posture classification (F1=0.91±0.03).This study demonstrates the potential of a 3-sensor lower body wearable solution (e.g. smart pants) that can identify proper sitting postures and exercises in multiple planes, suitable for low back pain. This technology has the potential to improve the effectiveness of LBP rehabilitation by facilitating quantitative feedback, early problem diagnosis, and possible remote monitoring.

High-Performance Control Simulation of PFC Converter for Electric Vehicle Charger

In order to solve the problems of low power factor and large harmonic pollution of some electrical equipment connected to the power grid, such as electric vehicle charger system, the author proposes a high-performance control simulation study of a PFC converter for electric vehicle charger. Using the staggered parallel boost power factor correction circuit topology of electric vehicle chargers as the front stage, its high power factor and low harmonic current characteristics can reduce the pollution to the power grid, and the detailed design process and loss analysis of the circuit are given. Through the digital control method and hardware optimization design, the loss is reduced, and the conversion efficiency of the power factor correction converter in the full power range is high, which meets the efficiency requirements of the platinum version and achieves the goal of energy saving and environmental protection. The test results show that the actual efficiency of the experimental prototype is 97.43%, 97.55%, and 97.36%, which are far higher than the efficiency requirements of the platinum version. Conclusion. The high-performance control of the PFC converter of the electric vehicle charger has certain guiding significance for the application in the electric vehicle.

Hardware Efficient Reconfigurable Digital Down Converter for Software Radio Receiver

ABSTRACT This paper describes a reconfigurable digital down converter (DDC) that can reduce the input sampling frequency from 128 MHz to an output of 1 MHz on a field-programmable gate array (FPGA) device. The proposed design employs a polyphase mixer followed by a half-band (HB) filter and a finite impulse response (FIR) filter. All the decimation filters involve polyphase architectures, enabling efficient hardware implementation. The polyphase mixer can reduce the high sampling rate frequency, and combining both HB and FIR filters results in a complex down-converted baseband spectrum. In addition, the modified HB filter reduces multiplier units, and the proposed FIR filter saves the delay elements. Using the optimal hardware description language (HDL) programming style, the design can further improve the area efficiency without sacrificing functionality. To evaluate the performance, the design has been implemented on the Kintex-7 Xilinx FPGA device. Experimental outcomes show that the proposed design significantly reduces hardware costs associated with other existing designs. Finally, a verification test certifies that the DDC has achieved a satisfactory spurious-free dynamic range (SFDR) of 115 dB. The high sampling rate and parallel processing capabilities of the proposed DDC make it an attractive solution for any software radio standard.

Automatic Creation of High-bandwidth Memory Architectures from Domain-specific Languages: The Case of Computational Fluid Dynamics

Numerical simulations can help solve complex problems. Most of these algorithms are massively parallel and thus good candidates for FPGA acceleration thanks to spatial parallelism. Modern FPGA devices can leverage high-bandwidth memory technologies, but when applications are memory-bound designers must craft advanced communication and memory architectures for efficient data movement and on-chip storage. This development process requires hardware design skills that are uncommon in domain-specific experts. In this article, we propose an automated tool flow from a domain-specific language for tensor expressions to generate massively parallel accelerators on high-bandwidth-memory-equipped FPGAs. Designers can use this flow to integrate and evaluate various compiler or hardware optimizations. We use computational fluid dynamics (CFD) as a paradigmatic example. Our flow starts from the high-level specification of tensor operations and combines a multi-level intermediate representation–based compiler with an in-house hardware generation flow to generate systems with parallel accelerators and a specialized memory architecture that moves data efficiently, aiming at fully exploiting the available CPU-FPGA bandwidth. We simulated applications with millions of elements, achieving up to 103 GFLOPS with one compute unit and custom precision when targeting a Xilinx Alveo U280. Our FPGA implementation is up to 25× more energy efficient than expert-crafted Intel CPU implementations.

Hardware Optimizations of Fruit-80 Stream Cipher: Smaller than Grain

Fruit-80, which emerged as an ultra-lightweight stream cipher with 80-bit secret key, is oriented toward resource-constrained devices in the Internet of Things. In this article, we propose area and speed optimization architectures of Fruit-80 on FPGAs. Our implementations include both serial and parallel structure and optimize area, power, speed, and throughput, respectively. The area optimization architecture aims to achieve the most suitable ratio of look-up-tables and flip-flops to fully utilize the reconfigurable unit. It also reuses NFSR and LFSR feedback functions to save resources for high throughput. The speed optimization architecture adopts a hybrid approach for parallelization and reduces the latency of long data paths by pre-generating primary feedback and inserting flip-flops. Besides, we recommend using the round key function to optimize serial or parallel implementations for Fruit-80 and using indexing and shifting methods for different throughput. In conclusion, our results show that the area optimization architecture occupies up to 35 slices on Xilinx Spartan-3 FPGA and 18 slices on Xilinx 7 series FPGA, smaller than that of Grain and other common stream ciphers. The optimal throughput/area ratio of the speed optimization architecture is 7.74 Mbps/slice, better than that of Grain v1, which is 5.98 Mbps/slice. The serial implementation of Fruit-80 with round key function occupies only 75 slices on Spartan-3 FPGA. To the best of our knowledge, the result sets a new record of the minimum area in lightweight cipher implementation on FPGA.

XNOR-Bitcount Operation Exploiting Computing-In-Memory With STT-MRAMs

This brief presents an energy-efficient and high-performance XNOR-bitcount architecture exploiting the benefits of computing-in-memory (CiM) and unique properties of spin-transfer torque magnetic RAM (STT-MRAM) based on double-barrier magnetic tunnel junctions (DMTJs). Our work proposes hardware and algorithmic optimizations, benchmarked against a state-of-the-art CiM-based XNOR-bitcount design. Simulation results show that our hardware optimization reduces the storage requirement (–50%) for each XNOR-bitcount operation. The proposed algorithmic optimization improves execution time and energy consumption by about 30% (78%) and 26% (85%), respectively, for single (5 sequential) 9-bit XNOR-bitcount operations. As a case study, our solution is demonstrated for shape analysis using bit-quads.

A 1.6-mW Sparse Deep Learning Accelerator for Speech Separation

Low-power deep learning accelerators (DLAs) on the speech processing enable real-time applications on edge devices. However, most of the existing accelerators suffer from high-power consumption and focus on image applications only. This article presents a low-power accelerator for speech separation through algorithm and hardware optimizations. At the algorithm level, the model is compressed with structured sensitivity as well as unstructured pruning, and further quantized to the shifted 8-bit floating-point format instead of the 32-bit floating-point format. The computations with the zero kernel and zero activation values are skipped by decomposition of the dilated and transposed convolutions. At the hardware level, the compressed model is then supported by an architecture with eight independent multipliers and accumulators (MACs) with a simple zero-skipping hardware to take advantage of the activation sparsity and low-power processing. The proposed approach reduces the model size by 95.44% and computation complexity by 93.88%. The final implementation with the TSMC 40-nm process can achieve real-time speech separation and consumes 1.6-mW power when operated at 150 MHz. The normalized energy efficiency and area efficiency are 2.344 TOPS/W and 14.42 GOPS/mm2, respectively.

A high speed reconfigurable architecture for softmax and GELU in vision transformer

AbstractTransformers have been widely used in various computer vision applications. Compared to traditional convolutional neural networks (CNNs), transformer's inference includes plenty of non‐linear operations, such as softmax and Gaussian error linear units (GELU). As the scale of transformers grows, an efficient hardware implementation of these operations is significant. However, the current works of computer vision neural network accelerators focus on CNN and less attention is paid to transformer. In addition, most current FPGA‐based softmax or GELU accelerators are not designed for vision transformer (ViT). To solve this problem, this work proposes a high speed reconfigurable accelerator. The architecture can support both softmax and GELU functions in ViT by reconfiguring the data path. This architecture on Xilinx XCVU37P is implemented through mathematical transformation and hardware optimization design, and achieve the performance of 102.4 Giga bits per second (Gbps) at 200 MHz. Experimental results show that the architecture achieves a very small accuracy loss in the ViT's inference by using fixed‐point 16‐bit quantization. Compared with existing accelerators, the design has greater throughput and area efficiency.

Evaluation of a Modular Approach to AES Hardware Architecture and Optimization

Evaluation of a Modular Approach to AES Hardware Architecture and Optimization

Теоретические аспекты принципов расчета струйных насосных станций и пути их совершенствования

The article presents analysis of the jet pump designs and methods of their improving, as well as technical approaches to their calculation, which is associated with a reasonable choice of an efficient variant, depending on the required accuracy of engineering calculations with optimal hardware support of pumping stations for solving specific oil and gas transportation tasks. According to the analysis results it has been inferred that one of the reasons for delay in application of jet pumping stations for lifting the fluid from the borehole space is the shortage of reliable surface-type pumping power stations, in particular, for driving the jet unit, as well as a compact set of equipment for purification and preliminary preparation of working fluid in the Russian Federation. For this reason, such units are mainly used for influencing the bottom-hole area, where the long-term permanent operation of jet pumping stations is not important, the mobile field pumping stations being possible as power plants.

F-LSTM: FPGA-Based Heterogeneous Computing Framework for Deploying LSTM-Based Algorithms

Long Short-Term Memory (LSTM) networks have been widely used to solve sequence modeling problems. For researchers, using LSTM networks as the core and combining it with pre-processing and post-processing to build complete algorithms is a general solution for solving sequence problems. As an ideal hardware platform for LSTM network inference, Field Programmable Gate Array (FPGA) with low power consumption and low latency characteristics can accelerate the execution of algorithms. However, implementing LSTM networks on FPGA requires specialized hardware and software knowledge and optimization skills, which is a challenge for researchers. To reduce the difficulty of deploying LSTM networks on FPGAs, we propose F-LSTM, an FPGA-based framework for heterogeneous computing. With the help of F-LSTM, researchers can quickly deploy LSTM-based algorithms to heterogeneous computing platforms. FPGA in the platform will automatically take up the computation of the LSTM network in the algorithm. At the same time, the CPU will perform the pre-processing and post-processing in the algorithm. To better design the algorithm, compress the model, and deploy the algorithm, we also propose a framework based on F-LSTM. The framework also integrates Pytorch to increase usability. Experimental results on sentiment analysis tasks show that deploying algorithms to the F-LSTM hardware platform can achieve a 1.8× performance improvement and a 5.4× energy efficiency improvement compared to GPU. Experimental results also validate the need to build heterogeneous computing systems. In conclusion, our work reduces the difficulty of deploying LSTM on FPGAs while guaranteeing algorithm performance compared to traditional work.

Using Augmented Reality for Visualizing Architectures of Software Modules

Nowadays the technology of augmented reality has become available for a wide audience of users because of a big number of software and hardware enhancements and optimizations done in the last years. The fact that the smartphone is a suitable and relatively cheap device having all the hardware required makes the technology even more accessible and thus widespread. Furthermore, the interaction with three-dimensional objects in space may have positive impact on user’s perception of information. These both facts make the technology of augmented reality a good choice for displaying complex data.The analysis of software plays a significant role in development as it is vital to keep the code clean and sustained all the time. Poor quality code may be unsustainable to the extent it must be fully replaced which results in big losses of resources. In terms of quality checks the analysis must be informative and consume as few resources as possible to be executed so that it is appropriate to perform it regularly. That is the reason for this process to be automated and made convenient to execute and percept.The new system for automatic software analysis is described in this article. ADAR (Architecture Displayer in Augmented Reality) software is best suitable for code coupling and cohesion analysis as it uses three-dimensional graph to display connectivity between parts of software module. High coupling and low cohesion might inform the developers of severe architectural mistakes that may lead to high code fragility. With the use of AR technology the result of high coupling detection analysis in the form of graph is presented in augmented reality to provide user the information in a highly intuitive way.This article also covers different approaches to graph visualization in three-dimensional space. The criteria that allow to achieve high level of aesthetics relative to this problem are stated in paper. The problem of using the force-directed algorithms in terms of high-aesthetic graph visualization is described in details and some arguments pro their usage are given.

Parameterizable Design on Convolutional Neural Networks Using Chisel Hardware Construction Language

This paper presents a parameterizable design generator on convolutional neural networks (CNNs) using the Chisel hardware construction language (HCL). By parameterizing structural designs such as the streaming width, pooling layer type, and floating point precision, multiple register-transfer level (RTL) implementations can be created to meet various accuracy and hardware cost requirements. The evaluation is based on generated RTL designs including 16-bit, 32-bit, 64-bit, and 128-bit implementations on field-programmable gate arrays (FPGAs). The experimental results show that the 32-bit design achieves optimal hardware performance when setting the same weights for estimating the quality of the results, FPGA slice count, and power dissipation. Although the focus is on CNNs, the approach can be extended to other neural network models for efficient RTL design.

Hardware optimization for photonic time-delay reservoir computer dynamics

Reservoir computing (RC) is one kind of neuromorphic computing mainly applied to process sequential data such as time-dependent signals. In this paper, the bifurcation diagram of a photonic time-delay RC system is thoroughly studied, and a method of bifurcation dynamics guided hardware hyperparameter optimization is presented. The time-evolution equation expressed by the photonic hardware parameters is established while the intrinsic dynamics of the photonic RC system is quantitively studied. Bifurcation dynamics based hyperparameter optimization offers a simple yet effective approach in hardware setting optimization that aims to reduce the complexity and time in hardware adjustment. Three benchmark tasks, nonlinear channel equalization (NCE), nonlinear auto regressive moving average with 10th order time lag (NARMA10) and Santa Fe laser time-series prediction tasks are implemented on the photonic delay-line RC using bifurcation dynamics guided hardware optimization. The experimental results of these benchmark tasks achieved overall good agreement with the simulated bifurcation dynamics modeling results.

FPGA-Based Vehicle Detection and Tracking Accelerator.

A convolutional neural network-based multiobject detection and tracking algorithm can be applied to vehicle detection and traffic flow statistics, thus enabling smart transportation. Aiming at the problems of the high computational complexity of multiobject detection and tracking algorithms, a large number of model parameters, and difficulty in achieving high throughput with a low power consumption in edge devices, we design and implement a low-power, low-latency, high-precision, and configurable vehicle detector based on a field programmable gate array (FPGA) with YOLOv3 (You-Only-Look-Once-version3), YOLOv3-tiny CNNs (Convolutional Neural Networks), and the Deepsort algorithm. First, we use a dynamic threshold structured pruning method based on a scaling factor to significantly compress the detection model size on the premise that the accuracy does not decrease. Second, a dynamic 16-bit fixed-point quantization algorithm is used to quantify the network parameters to reduce the memory occupation of the network model. Furthermore, we generate a reidentification (RE-ID) dataset from the UA-DETRAC dataset and train the appearance feature extraction network on the Deepsort algorithm to improve the vehicles' tracking performance. Finally, we implement hardware optimization techniques such as memory interlayer multiplexing, parameter rearrangement, ping-pong buffering, multichannel transfer, pipelining, Im2col+GEMM, and Winograd algorithms to improve resource utilization and computational efficiency. The experimental results demonstrate that the compressed YOLOv3 and YOLOv3-tiny network models decrease in size by 85.7% and 98.2%, respectively. The dual-module parallel acceleration meets the demand of the 6-way parallel video stream vehicle detection with the peak throughput at 168.72 fps.

High-Throughput Bit-Pattern Matching under Heavy Interference on FPGA

Bit-pattern matching is an important technological capability, used in many fields such as network intrusion detection (NID) and packet classification systems. Essentially, it involves the matching of an input bit pattern to a bit-pattern entry of a memory structure inside the system. Contemporary methods focus on the decomposition of the input bit pattern into smaller and more manageable parts, with the subsequent parallel processing of these elements. This fragmentation promotes the use of advanced pipeline techniques and hardware optimizations, enabling these methods to achieve very high throughputs and reasonable efficiency. However, the functionality of their respective circuits is limited to only performing pattern matching when there is no interference. In this article, we intend to present a circuit that performs pattern matching under heavy interference; instead of fragmentation, a more holistic approach will be adopted. To improve the throughput of the circuit, long bit sequences will be directly compared to many memory entries simultaneously. The minimization of hardware consumption and maximization of efficiency in these comparisons will be achieved with the use of novel hardware architecture that is based on pipelined adder trees and comparators. The platform of implementation is an FPGA (Field-Programmable Gate Array).

Memory-Tree Based Design of Optical Character Recognition in FPGA

As one of the fields of Artificial Intelligence (AI), Optical Character Recognition (OCR) systems have wide application in both industrial production and daily life. Conventional OCR systems are commonly designed and implement data computation on the basis of microprocessors; the performance of the processor relates to the effect of the computation. However, due to the “Memory-wall” problem and Von Neumann bottlenecks, the drawbacks of traditional processor-based computing for OCR systems are gradually becoming apparent. In this paper, an approach based on the Memory-Centric Computing and “Memory-Tree” algorithm has been proposed to perform hardware optimization of traditional OCR systems. The proposed algorithm was first designed in software implementation using C/C++ and OpenCV to verify the feasibility of the idea and then the RTL conversion of the algorithm was done using the Xilinx Vitis High Level Synthesis (HLS) tool to implement the hardware. This work chose Xilinx Alveo U50 FPGA Accelerator to complete the hardware design, which can be connected to the x86 CPU in the PC by PCIe to form heterogeneous computing. The results of the hardware implementation show that the system this work designed can recognize characters of English capital letters and numbers within 34.24 us. The power of FPGA is 18.59 W, which saves 77.87% of energy consumption compared to the 84 W of the processor in PC.

Algorithm and hardware co-design co-optimization framework for LSTM accelerator using quantized fully decomposed tensor train

Nowadays, from companies to academics, researchers across the world are interested in developing Deep Neural Networks (DNNs) due to their incredible feats in various applications, such as image recognition, playing complex games, and large-scale information retrieval such as web search. However, when people enjoy the advantages of DNNs, the high computational and power demands on resource-constrained electronic devices of the DNN model have received more attention. Optimizing the DNN model, such as model compression, is crucial to ensure wide deployment of DNNs and promote DNNs to implement most resource-constrained scenarios. Among many techniques, tensor train (TT) decomposition is considered a very promising technology. Although our previous efforts achieve (1) expanding limits of the number of multiplications eliminating all redundant computations; and (2) decomposing into multistage processing to reduce memory traffic, the potential of this work is not fully explored.In this paper, we investigate and demystify the TT decomposition within a thoughtful hardware mind. This paper develops an efficient hardware optimization methodology within a novel hardware solution. Two key merits will be achieved in this project: (1) it enables a novel approach to apply TT-decomposition on the entire LSTM model; (2) a much more efficient quantization method has been proposed at the hardware optimization level; (3) an efficient hardware accelerator that unitizes the hardware and algorithm co-design method has been designated.Based on these novelties, the proposed work can achieve 1.69× power reduction and 2.28× power efficiency (GOPS/W) in different workloads. In addition, compared to the state-of-the-art C-LSTM, it achieves 2.09× higher throughput, 3.67% accuracy increase, 2.45× power efficiency, and a 1.18× power reduction. The results show that our proposed accelerator exhibits significant advantages over state-of-the-art solutions.

BOHA: A High Performance VSLAM Backend Optimization Hardware Accelerator using Recursive Fine-Grain H-Matrix Decomposition and Early-Computing with Approximate Linear Solver

Visual simultaneous localization and mapping (VSLAM) technology has been used in many intelligent applications such autonomous car, unmanned aerial vehicle (UAV) and augmented reality (AR) for localization and trajectory generation. The VSLAM usually contains the frontend computation and the backend optimization. The backend optimization is an essential part of VSLAM which helps improve the precision and dominates the computation time ( 80 VSLAM. However, it includes large inner data dependency which is difficult to be accelerated using GPU. To address this issue, in this work, we propose a high performance VSLAM backend optimization hardware accelerator (named BOHA). Diverse design techniques have been proposed to reduce computation latency by avoiding the data redundancy in the backend optimization, including 1) a recursive fine-grain H-matrix decomposition computing architecture to improve the hardware utilization and reduce the data movement. 2) an early-computing technique with approximate linear solver to reduce the computation latency while maintaining high precision. 3) a twostage deep Schur elimination technique to reduce the computation latency. The proposed design has been implemented and evaluated on a Xilinx FPGA ZCU104 and achieves low computation latency (5.1 ms) with low trajectory error (0.27 state-of-the-art designs.