Hardware Emulation Research Articles

Avionics Graphics Hardware Performance Prediction with Machine Learning

Within the strongly regulated avionic engineering field, conventional graphical desktop hardware and software application programming interface (API) cannot be used because they do not conform to the avionic certification standards. We observe the need for better avionic graphical hardware, but system engineers lack system design tools related to graphical hardware. The endorsement of an optimal hardware architecture by estimating the performance of a graphical software, when a stable rendering engine does not yet exist, represents a major challenge. As proven by previous hardware emulation tools, there is also a potential for development cost reduction, by enabling developers to have a first estimation of the performance of its graphical engine early in the development cycle. In this paper, we propose to replace expensive development platforms by predictive software running on a desktop computer. More precisely, we present a system design tool that helps predict the rendering performance of graphical hardware based on the OpenGL Safety Critical API. First, we create nonparametric models of the underlying hardware, with machine learning, by analyzing the instantaneous frames per second (FPS) of the rendering of a synthetic 3D scene and by drawing multiple times with various characteristics that are typically found in synthetic vision applications. The number of characteristic combinations used during this supervised training phase is a subset of all possible combinations, but performance predictions can be arbitrarily extrapolated. To validate our models, we render an industrial scene with characteristic combinations not used during the training phase and we compare the predictions to those real values. We find a median prediction error of less than 4 FPS.

On Error Injection for NoC Platforms: A UVM-Based Generic Verification Environment

Error injection has become critically important for testing the reliability of newly designed hardware systems. Evaluating how a design under test (DUT) reacts to different error-injection methodologies is essential for verification engineers to design dependable universal verification methodology (UVM) scoreboards for error-detection purposes. The first main contribution of this paper is to decide on the feasibility and compatibility of some error-injection techniques when used with networks-on-chip (NoC) platforms for simulation and hardware emulation environments. We target a UVM-based error-injection and detection environment with reusable components. Proposed techniques, introducing both positive and negative test scenarios, are applied to two examples of NoC components: 1) a base router and 2) Daniel router. Base router is a simple case study to prove proposed schemes, whereas Daniel router is a complex reconfigurable open-source case study. Daniel router provides the ability to change router architecture with some parameters and applied algorithms. The second main contribution of this paper is to integrate a full UVM environment with various verification approaches. Target approaches include error injection and detection using reusable and generic UVM environment and components for NoC. Network response is inspected according to error type and methodology. Finally, the proposed UVM environment is used to test and verify an ${N}\,\,{\times }\,\,{N}\,\,2$ -D network composed of base routers or Daniel routers.

Virtual Verification and Validation of Automotive System

An integrated framework for Virtual Verification and Validation (VVV) for a complete automotive system is proposed. The framework can simulate/emulate the system on three levels: System on Chip (SoC), Electronic control unit (ECU) and system level. The framework emulates the real system including hardware (HW) and software (SW). It enhances the automotive V-cycle and allows co-development of the automotive system SW and HW. The procedure for debugging AUTOSAR application on the virtual platform (VP) is shown. SW and HW profiling is feasible with the presented methodology. Verification and validation of automotive embedded SW is also presented. The proposed methodology is efficient as the system complexity increases which shortens the development cycle of automotive system. It also provides fault injection capability. With HW emulation, co-debugging mechanism is demonstrated. A case study covering the framework capability is presented. The case study demonstrates the proposed framework and methodology to design, simulate, trace, profile and debug AUTOSAR SW using VPs.

An FPGA-Based Hardware Emulator for Neuromorphic Chip With RRAM

Neuromorphic chip with RRAM devices has been demonstrated as a promising computing platform for neural network-based applications. By directly mapping the weight matrices of neural networks onto RRAM-based crossbar arrays, high energy, and area efficiency can be achieved. However, the design of an RRAM-based neuromorphic chip faces many constraints due to the variability and limitations of RRAM. Simulation and emulation can help in the design of a neuromorphic chip prior to fabrication. However, software-based chip simulation on CPU is slow, especially for large-scale network-on-chip (NoC)-based chip design. In this paper, we present a hardware emulator on field-programmable gate array (FPGA) for an RRAM-based neuromorphic chip. Our emulator supports the emulation of static and dynamic variation of the RRAM-based crossbars used in the neural cores of a neuromorphic chip. Furthermore, an NoC is also implemented on FPGA to emulate the communication between the neural cores. Using the emulator, we show that effects, such as RRAM write and read noise and stuck-at faults affect the accuracy of an application on a neuromorphic chip. We also demonstrate the utility of the emulator in investigating NoC topologies, routing buffer depths, and neural core mappings.

Auto‐reclosing scheme with adaptive dead time control for extra‐high‐voltage transmission line

Discrimination between transient fault and permanent fault is contemporary problems for protection of transmission line. Auto-reclosure is one of the foremost solutions for the same. This study presents the development of auto-reclosure scheme using modified full-cycle discrete Fourier transform with adaptive dead time control. The discrimination between transient and permanent fault is done using differential voltage across the contacts of circuit breaker. Reclosing instance is identified by comparing absolute value of positive sequence voltage, phase difference and frequency difference with a respective preset threshold using synchronism check relay. The proposed scheme has been validated by simulating power system considering variation in fault location, fault clearance angle, fault resistance and load flow in PSCAD/EMTDC. The algorithm for the auto reclosing scheme is validated in MATLAB software. Real time emulation of the proposed algorithm is performed using AVR ATmega 328P controller on laboratory prototype. The test results of simulation and hardware emulation corroborate the efficacy of the proposed technique.

A Hardware Emulator for OLED Panels Applied to Lighting Systems

In this paper, a hardware emulator (HE) for organic light-emitting diodes (OLEDs) is proposed. Two OLED panels used in lighting applications are characterized based on a theoretical equivalent model (TEM). The objective is to better understand OLED operation and to infer about their electric static and dynamic behavior. From this, a HE able to represent the real behavior of an OLED panel using equivalent devices is proposed. The goal is to provide a useful tool for an adequate OLED driver design. In order to validate the HE, OLED samples were experimentally tested under static and dynamic operating conditions. The comparison between HE and OLED experimental results demonstrates a satisfactory accuracy.

Modeling and Emulation of a Rotating Paddle Type Wave Energy Converter

Torque-speed characteristics of an oscillating wave energy converter (WEC) is necessary to determine its optimal power point and to extract the corresponding design parameters for the generator and power converters used to generate power from the WEC. In this paper, analytical expressions for the mechanical torque on the WEC due to the oscillating surge of seawater are derived, and the dynamic model of the WEC is developed. A method for hardware emulation of the WEC is proposed by controlling the torque of an electric motor. The reference torque of the motor is derived by solving the mechanical dynamics of the WEC system in a real-time computing device considering a typical sea wave input. The emulated WEC dynamics is validated through variable loading on a generator coupled with the emulator. Experimental results support the existence of an optimal power point of the derived WEC model.

A Novel 3D Non-Stationary Wireless MIMO Channel Simulator and Hardware Emulator

In this paper, a new WINNER+-based 3-D non-stationary geometry-based stochastic model (GBSM) for multiple-input multiple-output channels is proposed, as well as extended evolving algorithms of time-variant channel parameters. Meanwhile, important statistical properties of the channel model, i.e., time-variant autocorrelation function, time-variant cross-correlation function, and time-variant Doppler power spectrum density are derived and analyzed. Moreover, we propose an efficient hardware implementation method, namely, sum-of-frequency-modulation (SoFM) method, to generate non-stationary channel coefficients. By utilizing compact hardware architecture with SoFM modules, the proposed 3-D non-stationary GBSM is realized on a field-programmable gate array hardware platform. Simulations and hardware measurement results demonstrate that our proposed channel simulator and emulator can get more accurate and realistic Doppler frequency than those of the existing models. In addition, hardware measurements of statistical properties are also well consistent with the corresponding theoretical ones, which verify the correctness of both the hardware emulation scheme and theoretical derivations.

Emulation of chemical stimulus triggered head movement in the C. elegans nematode

For a considerable time, it has been the goal of computational neuroscientists to understand biological nervous systems. However, the vast complexity of such systems has made it very difficult to fully understand even basic functions such as movement. Because of its small neuron count, the C. elegans nematode offers the opportunity to study a fully described connectome and attempt to link neural network activity to behaviour. In this paper a simulation of the neural network in C. elegans that responds to chemical stimulus is presented and a consequent realistic head movement demonstrated. An evolutionary algorithm (EA) has been utilised to search for estimates of the values of the synaptic conductances and also to determine whether each synapse is excitatory or inhibitory in nature. The chemotaxis neural network was designed and implemented, using the parameterisation obtained with the EA, on the Si elegans platform a state-of-the-art hardware emulation platform specially designed to emulate the C. elegans nematode.

A Real-Time Heterogeneous Emulator of a High-Fidelity Utility-Scale Variable-Speed Variable-Pitch Wind Turbine

Wind energy has the highest development rates of renewables. The increasing complexity of wind turbine (WT) systems requires careful analysis and design with thorough testing and certification procedures. Hardware emulators contribute to safe and cost-effective assessment and testing of WT in research and industry. Most of the available emulators concentrate on emulating electrical subsystems with simplified mechanical models. In this paper, a real-time (RT) heterogeneous emulator that combines RT discrete-time step simulation and a high-fidelity linear parameter-varying model of a utility-scale WT system is proposed and implemented on a heterogeneous CPU/GPU platform. The RT emulator is built on an embedded NVIDIA Jetson TK1 board for a National Renewable Energy Laboratory 5-MW WT as a case study. The proposed emulator is capable of further integration of electrical models and control systems of WT.

Precise Implementation of CDTA

The Current Differencing Transconductance Amplifier (CDTA) is a popular active building block for analog signal processing. Since it is not available as a commercial IC, most of the CDTA applications are verified only via simulations or the CDTA is implemented by commercial circuits. The paper deals with CDTA implementation, emphasizing the accuracy, linearity, and dynamic range of the processed signals, and low power consumption. Such a CDTA can be useful wherever these requirements are more relevant than the speed and bandwidth, typically for implementing hardware emulators of memristive systems.

Duality of Complex Systems Built from Higher‐Order Elements

The duality of nonlinear systems built from higher‐order two‐terminal Chua’s elements and independent voltage and current sources is analyzed. Two different approaches are now being generalized for circuits with higher‐order elements: the classical duality principle, hitherto restricted to circuits built from R‐C‐L elements, and Chua’s duality of memristive circuits. The so‐called storeyed structure of fundamental elements is used as an integrating platform of both approaches. It is shown that the combination of associated flip‐type and shift‐type transformations of the circuit elements can generate dual networks with interesting features. The regularities of the duality can be used for modeling, hardware emulation, or synthesis of systems built from elements that are not commonly available, such as memristors, via classical dual elements.

A Multicore Fault Injection Framework for Soft Errors on DSP

In the field of space computing, DSP is more and more used for its high performance. Like other non-radiation-resistant chips, COTS DSP is easily affected by high-energy particle irradiation in the space environment, which can prone to transient faults, also known as soft errors. Soft error is one of the serious problems to the reliability of space computing. To evaluate the reliability of the software system based on COTS DSP, we designed MDSPFI, a new Fault Injection (FI) framework based on DSP C6678. As an emulation-based FI framework, MDSPFI is much more efficient in performance than pure SWIFI, and has higher controllability than pure hardware implemented FI tools. We designed FI script as autonomous emulation, thus, avoiding the intensive communication between the host and the emulation platform. Moreover, we accelerate the average per-experiment runtime by running on hardware emulator as well as conducting multithreaded execution with the multicore architecture, and reduces the FI experiment count by adopting the Fault pruning techniques. Experimental results show that MDSPFI has fairly well correctness and effectiveness.

Hardware emulation of stochastic p-bits for invertible logic

The common feature of nearly all logic and memory devices is that they make use of stable units to represent 0’s and 1’s. A completely different paradigm is based on three-terminal stochastic units which could be called “p-bits”, where the output is a random telegraphic signal continuously fluctuating between 0 and 1 with a tunable mean. p-bits can be interconnected to receive weighted contributions from others in a network, and these weighted contributions can be chosen to not only solve problems of optimization and inference but also to implement precise Boolean functions in an inverted mode. This inverted operation of Boolean gates is particularly striking: They provide inputs consistent to a given output along with unique outputs to a given set of inputs. The existing demonstrations of accurate invertible logic are intriguing, but will these striking properties observed in computer simulations carry over to hardware implementations? This paper uses individual micro controllers to emulate p-bits, and we present results for a 4-bit ripple carry adder with 48 p-bits and a 4-bit multiplier with 46 p-bits working in inverted mode as a factorizer. Our results constitute a first step towards implementing p-bits with nano devices, like stochastic Magnetic Tunnel Junctions.

アナデジ混載オシレータLSIによる分散PLLネットワークのハードウェアエミュレーション(アナログ・デジアナ・センサ, 通信用LSI)

アナデジ混載オシレータLSIによる分散PLLネットワークのハードウェアエミュレーション(アナログ・デジアナ・センサ, 通信用LSI)

Dynamic Variable Time-Stepping Schemes for Real-Time FPGA-Based Nonlinear Electromagnetic Transient Emulation

Electromagnetic transient (EMT) simulation of nonlinear elements in power systems is a particular challenge due to the requirements of an accurate representation and an efficient solution. The existing real-time simulators utilize a piecewise linear representation along with a fixed time step for the solution of nonlinear elements. This paper proposes the detailed methodologies for applying variable time stepping to real-time EMT simulation to improve the simulation accuracy and efficiency. The challenges, the feasible solutions, and corresponding restrictions of applying various variable time-stepping schemes along with nonlinear element solution methods in real time are discussed. The offline simulation and the real-time hardware emulation of two case studies, a full-bridge diode circuit and a power transmission system, are presented. The case studies were implemented on the field-programmable gate array device (Xilinx Virtex-7 XC7VX485T) in real time using high-level synthesis tool to achieve a parallelized and pipelined hardware design with minimum coding effort. The real-time emulation results captured by an oscilloscope are validated against the offline simulation on Saber and PSCAD/EMTDC software tools.

Memory-Centric Reconfigurable Accelerator for Classification and Machine Learning Applications

Big Data refers to the growing challenge of turning massive, often unstructured datasets into meaningful, organized, and actionable data. As datasets grow from petabytes to exabytes and beyond, it becomes increasingly difficult to run advanced analytics, especially Machine Learning (ML) applications, in a reasonable time and on a practical power budget using traditional architectures. Previous work has focused on accelerating analytics readily implemented as SQL queries on data-parallel platforms, generally using off-the-shelf CPUs and General Purpose Graphics Processing Units (GPGPUs) for computation or acceleration. However, these systems are general-purpose and still require a vast amount of data transfer between the storage devices and computing elements, thus limiting the system efficiency. As an alternative, this article presents a reconfigurable memory-centric advanced analytics accelerator that operates at the last level of memory and dramatically reduces energy required for data transfer. We functionally validate the framework using an FPGA-based hardware emulation platform and three representative applications: Naïve Bayesian Classification, Convolutional Neural Networks, and k-Means Clustering. Results are compared with implementations on a modern CPU and workstation GPGPU. Finally, the use of in-memory dataset decompression to further reduce data transfer volume is investigated. With these techniques, the system achieves an average energy efficiency improvement of 74× and 212× over GPU and single-threaded CPU, respectively, while dataset compression is shown to improve overall efficiency by an additional 1.8× on average.

A study of reduced numerical precision to make superparameterization more competitive using a hardware emulator in the OpenIFS model

AbstractThe use of reduced numerical precision to reduce computing costs for the cloud resolving model of superparameterized simulations of the atmosphere is investigated. An approach to identify the optimal level of precision for many different model components is presented, and a detailed analysis of precision is performed. This is nontrivial for a complex model that shows chaotic behavior such as the cloud resolving model in this paper. It is shown not only that numerical precision can be reduced significantly but also that the results of the reduced precision analysis provide valuable information for the quantification of model uncertainty for individual model components. The precision analysis is also used to identify model parts that are of less importance thus enabling a reduction of model complexity. It is shown that the precision analysis can be used to improve model efficiency for both simulations in double precision and in reduced precision. Model simulations are performed with a superparameterized single‐column model version of the OpenIFS model that is forced by observational data sets. A software emulator was used to mimic the use of reduced precision floating point arithmetic in simulations.

Memristor-based neural networks: Synaptic versus neuronal stochasticity

In neuromorphic circuits, stochasticity in the cortex can be mapped into the synaptic or neuronal components. The hardware emulation of these stochastic neural networks are currently being extensively studied using resistive memories or memristors. The ionic process involved in the underlying switching behavior of the memristive elements is considered as the main source of stochasticity of its operation. Building on its inherent variability, the memristor is incorporated into abstract models of stochastic neurons and synapses. Two approaches of stochastic neural networks are investigated. Aside from the size and area perspective, the impact on the system performance, in terms of accuracy, recognition rates, and learning, among these two approaches and where the memristor would fall into place are the main comparison points to be considered.

Scaled Hardware Implementation of a Full Conversion Wind Turbine for Low Frequency AC Transmission

Low Frequency AC Transmission (LFAC) at 16.7Hz is seen by many as a realistic cost effective alternative to VSC-HVDC for the interconnection of offshore wind. The implementation of the LFAC transmission system envisaged in this work requires the use of full conversion wind turbines which output power to a 16.7Hz collection network, which requires some redesign of the back to back converter typically used in such turbines. This paper presents the real time scaled hardware emulation of a full conversion wind turbine connected to a 16.7Hz grid. The study concentrates on both software control strategies for the converters, highlighting the performance of the generator for the export of power to the grid. The LFAC grid side PLL (Phase Locked Loop) is also introduced – synchronizing with the imposed 16.7Hz. An emulation test bed is built and demonstrated in hardware - with the system successfully exporting power to the LFAC grid. This contribution highlights the ability to design a wind turbine network offshore to interface to an LFAC transmission system.