Hardware Emulation Research Articles

A virtual storage environment for SSDs and HDDs in Xen hypervisor

Nowadays, virtualization is a popular technology to provide an abstract hardware emulation due to the increasing hardware speed and capabilities such as multi-core CPUs, large-size main memory, and high-bandwidth networking. Virtualization technology enables multiple virtual machines to run on a physical machine, where each virtual machine can run independently and own its operating system. In particular, I/O performance will be an important factor of virtualization technology. Current popular storage devices contain traditional hard-disk drives (HDDs) and solid-state drives (SSDs). Although HDDs can provide a more economical solution than SSDs, SSDs can provide high I/O performance and power saving, especially for random I/O accesses. In the paper, we will build a virtual storage environment for SSDs and HDDs in Xen hypervisor. With the proposed virtual storage environment in Xen hypervisor, we can receive and analyze I/O requests from multiple virtual machines, and perform I/O requests to any physical storage devices. According to the experimental results, the proposed method can include both SSDs (i.e., fast access) and HDDs (i.e, low cost) in virtualization environment. Overall, the proposed method can provide an adjustment mechanism in I/O performance for those (soft real-time) applications that require high I/O performance in virtualization environment.

Reduced-Complexity Min-Sum Algorithm for Decoding LDPC Codes With Low Error-Floor

This paper proposes a low-complexity min-sum algorithm for decoding low-density parity-check codes. It is an improved version of the single-minimum algorithm where the two-minimum calculation is replaced by one minimum calculation and a second minimum emulation. In the proposed one, variable correction factors that depend on the iteration number are introduced and the second minimum emulation is simplified, reducing by this way the decoder complexity. This proposal improves the performance of the single-minimum algorithm, approaching to the normalized min-sum performance in the water-fall region. Also, the error-floor region is analyzed for the code of the IEEE 802.3an standard showing that the trapping sets are decoded due to a slow down of the convergence of the algorithm. An error-floor free operation below BER=10 -15 is shown for this code by means of a field-programmable gate array (FPGA)-based hardware emulator. A layered decoder is implemented in a 90-nm CMOS technology achieving 12.8 Gbps with an area of 3.84 mm 2 .

A Real-Time Nonlinear Hysteretic Power Transformer Transient Model on FPGA

A transformer is the most widely used equipment in power systems to transfer energy from one circuit to another. For real-time electromagnetic transient simulation, this paper presents a digital hardware emulation of the power transformer on a field programmable gate array. The linear model of the transformer is based on the admittance matrix approach. Detailed real-time modeling of the transient nonlinearities, including hysteresis phenomena, is carried out based on the Preisach theory. The nonlinear solution in real time is undertaken using a full Newton iteration. All the hardware modules for the transformer emulation were developed in VHDL. The model is fully parallelized and pipelined to achieve the lowest latency and the smallest hardware resource consumption. Real-time results on the oscilloscope are compared with off-line results from the ATP software.

Hardware emulation of quantum circuits based on Toffoli gates

This work presents the design of a hardware architecture for the emulation of quantum circuits based on Toffoli gates allowing the emulation of more than 50 qubits. The state of the system is obtained processing each basis state by means of the functions determined by the quantum gates for each qubit; the time required to execute the emulation grows exponentially only with the number of qubits that are used to generate a superposition of states, but not with the total amount of qubits of the system as occurs when the conventional matrix representation is used. Additionally, an array of processing units was designed to decrease the execution time. The synthesis results allow concluding that 9.35 seconds are required to emulate the 8-bit modular exponentiation, which uses 48 qubits, 155,312 quantum gates and requires processing 131,072 basis states. Furthermore these results allow estimating that 256 processing units of 52 qubits can be implemented in the FPGA EP3C120F780I7.

Battery Emulation for Power-HIL Using Local Model Networks and Robust Impedance Control

Battery emulation with a controllable high-power dc supply enables repeatable hardware-in-the-loop testing of powertrains for hybrid and electric vehicles. For this purpose, not only the power flow but also the nonlinear characteristic and dynamic impedance of batteries need to be emulated. In this paper, nonlinear local model networks are used to obtain dynamic battery models with high fidelity that can be computed in real time. This approach also allows the extraction of local linear impedance models for high-bandwidth impedance emulation, leading to a tighter coupling between the test bed and simulation model with predictable closed-loop dynamics. A model predictive controller that achieves optimal control with adherence to system constraints is extended to impedance control and robustness against constant power loads. This results not only in superior dynamic performance but also in stable dc-bus voltage control even for testing of tightly controlled electric motor inverters with negative differential input resistance. Since the controller design is based on a model of the test bed setup including the virtual battery model, emulator hardware, and input characteristics of the powertrain under test, it is possible to systematically analyze stability.

Hardware Emulation Building Blocks for Real-Time Simulation of Large-Scale Power Grids

Hardware Emulation Building Blocks for Real-Time Simulation of Large-Scale Power Grids

Hardware Emulation Building Blocks for Real-Time Simulation of Large-Scale Power Grids

This paper proposes digital hardware building block concept for emulating power system networks on field-programmable gate arrays (FPGAs) in real time. Basic hardware emulation building blocks (HEBBs) for machines, transmission lines, nonlinear elements, and loads are presented to demonstrate how real-time simulation can be achieved for realistic power systems. All of the hardware modules were developed using the VHDL language for portability and extensibility. Employing multiple FPGAs, a large-scale power system consisting of 1260 three-phase buses is modeled in detail in real time to show both electromagnetic transients and electromechanical dynamics in the system. The advantage of HEBB-based modeling is that the design and development of new technologies can be accelerated by utilizing massive real-time digital simulators capable of modeling multiscale and multidomain dynamics.

Metrics for the Measurement of the Quality of Stimuli in Radiation Testing Using Fast Hardware Emulation

Radiation Testing of unstructured digital circuits presents an extended set of difficulties related with detection and propagation of the faults to the primary outputs. Stimuli have to be chosen thinking on the possibility of propagating the faults through the logic to the primary outputs. Moreover, the set of stimuli should be selected to enhance the observability of both the time and location of the internal faults.

Novel approach to measurement-based load modeling via analog and Jacobi-based methods

This paper addresses a concrete problem in the field of power engineering. Although measurement-based modeling techniques have potential to drastically improve the quality of load representation in power system studies and positively affect results, they are not applied (in industry) for reasons of computational complexity. These limitations stem from the optimization methods (e.g. Newton–Raphson) and hardware implementations (e.g. digital computer) generally employed. In this work, the authors examine a simple, alternative method which relies on Jacobi optimization and analog emulation hardware to reduce computational complexity, facilitate online applications, and make measurement-based load modeling more attractive to utilities and independent system operators (ISO’s). They hypothesize and later demonstrate that the alternative will yield results comparable to that of traditional methods.

Integral form 4-D light field filters using Xilinx FPGAs and 45 nm CMOS technology

Four-dimensional (4-D) infinite impulse response frequency hyper-planar filter and a digital VLSI architecture for real time light field based depth filtering applications is proposed. A signal flow graph based on discrete spatial integrators is introduced, which leads to improved sensitivity properties for perturbations in filter coefficients. First order sensitivity analysis of filter transfer function shows a 92.9 % reduction of maximum gain error in frequency response with 12 bits of fractional precision, when compared with a direct-form architecture. Prototype FPGA hardware-in-the-loop co-simulations are performed for two different light field geometries. Register transfer level design validation is carried out via FPGA hardware emulation with a host computer providing memory buffers, and the full-design emulation is carried out on a standalone Berkely Emulation Engine (BEE3), operating at 36.44 and 37.31 MHz for the two light field geometries, respectively. 45 nm CMOS implementation is carried out up to the synthesis level, yielding operating frequencies of 154.4 and 153.3 MHz (correspondingly frame rates of 1.15 and 18.286 Hz) for the two light field geometries, respectively.

Multi‐FPGA digital hardware design for detailed large‐scale real‐time electromagnetic transient simulation of power systems

Large-scale electromagnetic transient simulation of power systems in real-time using detailed modelling is computationally very demanding. This study introduces a multi-field programmable gate array (FPGA) hardware design for this purpose. A functional decomposition method is proposed to map FPGA hardware resources to system modelling. This systematic method lends itself to fully pipelined and parallel hardware emulation of individual component models and numerical solvers, while preserving original system characteristics without the need for extraneous components to partition the system. Proof-of-concept is provided in terms of a 3-FPGA and 10-FPGA real-time hardware emulation of a three-phase 42-bus and 420-bus power systems using detailed modelling of various system components and iterative non-linear solution on a 100 MHz FPGA clock. Real-time results are compared with offline simulation results, and conclusions are derived on the performance and scalability of this multi-FPGA hardware design.

Gallager B Decoder on Noisy Hardware

Conventional communications theory assumes that the data transmission is noisy but the processing at the receiver is entirely error-free. Such assumptions may have to be revisited for advanced (silicon) technologies in which hardware failures are a major concern at the system-level. Hence, it is important to characterize the performance of a communication system with both noisy processing components and noisy data transmission. Coding systems based on low-density parity check (LDPC) codes are widely used for a variety of applications. In this paper, we focus on probabilistic analysis of the LDPC Gallager B decoder built out of faulty components. Using the density evolution technique, we find approximations for the optimal threshold of the decoder and the symbol error rate (SER) of the decoded sequence as functions of both the channel error rate and error rates of the decoder components, for both binary and non-binary regular LDPC codes. Furthermore, we study the convergence of the output SER and the decoding threshold of the decoder for different ranges of error rates. We verify our results using MATLAB simulations and hardware emulation of noisy decoders. Results presented in this paper can serve as systematic design guidelines in resource allocation for noisy decoders. Informed resource allocation is of particular relevance to emerging data storage and processing applications that need to maintain high levels of reliability despite hardware errors in advanced technologies.

SOC HW/SW co‐verification based debugging technique

PurposeIncreasingly complex and sophisticated VLSI design, coupled with shrinking design cycles, requires shorter verification time and efficient debug method. Logic simulation provides SoC verification with full controllability and observability, but it suffers from very slow simulation speed for complex design. Using hardware emulation such as FPGA can have higher simulation speed. However, it is very hard to debug due to its poor visibility. SOC HW/SW co‐verification technique seems to draw a balance, but Design Under Test (DUT) still resides in FPGA and remains hard for debugging. The purpose of this paper is to study a run‐time RTL debugging methodology for a FPGA‐based co‐verification system.Design/methodology/approachThe debugging tools are embedded in HDL simulator using Verilog VPI callback, so signals of testbench and internal nodes of DUT can be observed in a single waveform and updated as simulation runs, making debugging more efficient. The proposed debugging method connects internal nodes directly to a PCI‐extended bus, instead of inserting extra scan‐chain logic, so the overhead for area is reduced.FindingsThis method provides internal nodes probing on an event‐driven co‐verification platform and achieves full observability for DUT. The experiment shows that, compared with a similar method, the area overhead for debug logic is reduced by 30‐50 per cent and compile time is shortened by 40‐70 per cent.Originality/valueThe proposed debugging technique achieves 100 per cent observability and can be applied to both RTL and gate‐level verification. The debugging tool is embedded into HDL simulator using Verilog VPI callback, so DUT signals are displayed together with testbench signals in the same waveform viewer. New value of DUT signal is read from FPGA whenever it changes, which allows run‐time debug.

Development of an HT PEM Fuel Cell Emulator Using a Multiphase Interleaved DC–DC Converter Topology

This paper presents a new emulator topology for a high-temperature (HT) proton-exchange membrane (PEM) fuel cell (FC). Emulators are used to predict FC behavior and facilitate development of the power-conditioning subsystems. In this paper, the high-temperature system is modeled and emulated both in the steady state and transient domains. The model is tailored to operate effectively in real time on the emulator hardware and to deliver acceptable performance during steady-state and dynamic conditions. In particular, a two-stage approach is applied to the design of the emulator hardware. The first stage is based on a multiphase interleaved converter, capable of maximizing ripple cancellation, while ensuring rapid dynamic performance through the use of reduced filter components. These benefits are only apparent by operating the converter at its critical duty ratio. This is achieved through the introduction of a power-stage converter, which tracks the steady-state behavior of the FC, allowing the multiphase converter to account for the rapid transient behavior. This operating principle improves the quality of the output dc voltage and dynamic performance beyond that achieved by conventional emulator topologies. The experimental results of the FC stack, HT PEM FC model and emulator are presented to confirm the performance of the proposed system.

Vector mode based hardware acceleration and emulation for LDPC application

PurposeWith the rapid development of integrated circuits, verification of SOC chips has become a great challenge due to its integration and complexity. Traditional software‐based simulation methodology cannot meet verification needs. Therefore, FPGA‐based hardware acceleration technologies are requested in SOC verification. The classic methodology of hardware acceleration downloads the DUT (Device under Test) to the FPGA, while part of RTL codes and test bench is still run on the simulator in the workstation. Research found that the speed bottleneck of this methodology is mostly caused by the ping‐pong mode of data transmission between workstation software and the FPGA emulator, thus resulting in that channel transmission time takes too much proportion of total time. The purpose of this paper is to present a vector mode based hardware/software co‐emulation methodology, which leverages a pipeline structure to transmit, receive and buffer data. This methodology reduces the communication overhead by carrying out a parallel mechanism in that while user's design is under test in the emulator, signal data are transmitting in the channel simultaneously, thus increasing the speed of hardware acceleration and emulation.Design/methodology/approachThe methodology of hardware acceleration proposed by this paper intercepts data for once from the emulation process of a traditional platform as test bench and utilizes direct memory access (DMA) channel to speed up data transfer, as well as increasing reasonable data caching mechanism, which reduces the ratio of channel transmission time in the entire emulation time, achieving accelerating emulation.FindingsThe proposed methodology and traditional hardware acceleration approach were tested on a quasi‐cyclic low‐density parity‐check (LDPC) decoder. Experiment results indicate that the proposed method can increase communication throughput 140 times compared with the traditional approach.Originality/valueA vector mode based hardware/software co‐emulation methodology is presented in the paper. Higher communication throughput can be achieved by carrying out a parallel mechanism, as well as leveraging a pipeline structure to transmit, receive and buffer data.

Accelerating Emulation and Providing Full Chip Observability and Controllability at Run-Time

Performing hardware emulation on FPGAs is a significantly faster and more accurate approach for the verification of complex designs than software simulation. Therefore, hardware Simulation Accelerator and Emulator co-processor units are used to offload calculation-intensive tasks from the software simulator. However, the communication overhead between the software simulator and the hardware emulator is becoming a new critical bottleneck. Moreover, in a hardware emulation environment it is impossible to bring outside of the chip a large number of internal signals for verification purposes. Therefore, on-chip observability has become a significant issue. In our work we tackle both aforementioned problems. First, we deploy a novel emulation framework that automatically transforms into synthesizable code certain HDL parts of the testbench, in order to offload them from the software simulator and, more importantly, minimize the aforementioned communication overhead. Next, we extend this architecture by adding multiple fast scan-chain paths in the design in order to provide full circuit observability and controllability on the fly. In this paper, we briefly describe our approach for reducing the communication overhead problem, and present, for the first time, our complete innovative system which offers extensive observability and controllability in complex Design Under Tests (DUTs).

Compact Circuit Model and Hardware Emulation for Floating Memristor Devices

A compact circuit model and physical hardware emulation for floating memristors are presented. By utilizing memristor 'resistance' as a state variable, and constructing a hardware emulator using a low-complexity modular structure, the model-based emulation can replicate diverse behaviors of different device types. Our hardware emulator for a voltage-actuated, threshold sensitive, two-terminal, floating memristor demonstrates experimentally memristor dynamics. The emulator is capable of computing any arithmetic operations without any disturbance associated with composition of modular structures.

Complex Simulation Model of Microturbine Unit

The paper deals with a mathematical model suitable for the hardware emulator of a microturbine power unit, which serves the design, optimization, and verification of control equipment. The emulator interface signals mimic the operation of a real turbine including the electrical parameters of interfaces. A system of algebraic-differential equations representing the turbine model is formulated such that it allows applying an explicit solver with a predictable amount of operations to obtain the next time step, which is important for the real-time simulation. The model includes the starter motor, generator, gearbox, and single-shaft gas microturbine. In addition to the normal operational performance the instrument allows simulating various faults.

Introducing Intelligent Agents Potential into a competent Integral Multi-Agent Sensor Network Simulation Architecture Design

During this research we spot several key issues concerning WSN design process and how to introduce intelligence in the motes. Due to the nature of these networks, debugging after deployment is unrealistic, thus an efficient testing method is required. WSN simulators perform the task, but still code implementing mote sensing and RF behaviour consists of layered and/or interacting protocols that for the sake of designing accuracy are tested working as a whole, running on specific hardware. Simulators that provide cross layer simulation and hardware emulation options may be regarded as the last milestone of the WSN design process. Especially mechanisms for introducing intelligence into the WSN decision making process but in the simulation level is an important aspect not tackled so far in the literature at all. The herein proposed multi-agent simulation architecture aims at designing a novel WSN simulation system independent of specific hardware platforms but taking into account all hardware entities and events for testing and analysing the behaviour of a realistic WSN system. Moreover, the design herein outlined involves the basic mechanisms, with regards to memory and data management, towards Prolog interpreter implementation in the simulation level.

POWER-MODES

Innovation cycles have been shortening significantly during the last years. This process puts tremendous pressure on designers of embedded systems for security-or reliability-critical applications. Eventual design problems not detected during design time can lead to lost money, confidentiality, or even loss of life in extreme cases. Therefore it is of vital importance to evaluate a new system for its robustness against intentionally and random induced operational faults. Currently this is generally done using extensive simulation runs using gate-level models or direct measurements on the finished silicon product. These approaches either need a significant amount of time and computational power for these simulations or rely on existing product samples. This article presents a novel system evaluation platform using power emulation and fault injection techniques to provide an additional tool for developers of embedded systems in security-and reliability-critical fields. Faults are emulated using state-of-the-art fault injection methods and a flexible pattern representation approach. The resulting effects of these faults on the power consumption profile are estimated using state-of-the-art power emulation hardware. A modular system augmentation approach provides emulation flexibility similar to fault simulation implementations. The platform enables the efficient evaluation of new hardware or software implementations of critical security or reliability solutions at an early development phase.