Hardware Description Language Research Articles

Deep Learning Algorithm Analysis of Potato Disease Classification for System on Chip Implementation

Recently, every aspect of human existence has been affected by modern technologies including agriculture. The broad range of crops has witnessed setbacks in different capacities due to climate change among other factors, hence leading to diseases and infections; thereby leading to negatively impacted nutrition. This work uses a deep learning algorithm to investigate the classification of potato diseases as a case study which can be leveraged on by other agricultural products for reference. Potatoes play a vital role in global agriculture, constituting a significant portion of fresh produce consumption. In southern Africa, potatoes hold particular importance, comprising 39% of total fresh produce consumption. However, the industry faces challenges from diseases such as early blight and late blight, resulting in substantial yield losses. Early detection is crucial, prompting the exploration of Convolutional Neural Networks (CNNs) for their disease classification capabilities. CNNs have shown excellent results in plant disease classification based on image data set. This study proposes the potential of aligning existing software-based Central Processing Units (CPUs) and Graphic Processing Units (GPUs) with FPGA-based potato disease classification using CNNs. To this end, five CNN models were trained on the Plant Village dataset for analysis. The models were compared using various performance metrics such as sensitivity, F1-Score, precision and recall. Based on the analysis the most suitable CNN model for FPGA implementation was selected. The chosen model was optimized for size using quantization technique. Subsequently the model was converted to Hardware Description Language (HDL) using Vitis High level synthesis (HLS) tool performance in terms of resources required to implement the model in System on Chip (SoC) was analysed.

Detecting Vulnerability in Hardware Description Languages: Opcode Language Processing

Detecting Vulnerability in Hardware Description Languages: Opcode Language Processing

Fast synchronization with enhanced switching control for grid-tied single-phase square wave inverter using FPGA

Research on grid synchronization has been conducted worldwide by researchers in conjunction with the development of innovative technologies, such as dedicated short-range communication (DSRC) and cellular vehicle-to-everything (C-V2X). However, grid-connected inverters face several challenges, mainly the mismatch in voltage amplitude, frequency, and phase angle, as well as grid voltage disturbance and grid faults. Thus, the control algorithm of this research mainly focused on a half-cycle algorithm to design an enhanced digital switching control for fast synchronization using an FPGA. The control algorithm was developed based on zero-crossing detection (ZCD) and digital phase-locked loop (PLL) modeling techniques using the hardware description language (HDL) and a combination of digital logic blocks in Quartus II software, where the proposed switching was applied using the square-wave switching technique through a 300-watt full-bridge experimental prototype. The performance of the proposed technique was studied, where the total harmonic distortion (THD) for voltage and current resulted in a percentage reduction of 89.29% and 78.05% for voltage and current, respectively, after filter implementation. Also, the resulting signal synchronized in every half cycle and matched the voltage amplitude, frequency, and phase angle of the grid signal in 10 ms.

Accelerating handwritten number classifier with pipelined Multiply-Accumulate units in neural networks

This research project explores the development and assessment of a Handwritten Number Classifier based on Neural Networks, employing the widely used MNIST dataset. The primary objective of this study is to enhance computational efficiency, and to achieve this, it concentrates on integrating and contrasting non-pipelined and pipelined structures within the Multiply-Accumulate (MAC) unit. The initial phase involved conducting MATLAB simulations, which yielded promising results regarding the accuracy of weight calculations. Subsequently, Hardware Description Language (HDL) testing was carried out to further validate the classifiers performance. In the HDL testing phase, the classifier incorporating the pipelined MAC unit demonstrated a substantial 42.9% enhancement in processing speed when compared to its non-pipelined counterpart. These results highlight the potential advantages of employing pipeline processing in neural network architectures, emphasizing its effectiveness in achieving faster and more efficient image classification, particularly when dealing with extensive datasets. In conclusion, this research project not only presents valuable insights into improving the efficiency of neural network-based image classifiers but also lays the groundwork for potential future endeavors. These future directions may include adapting the classifier to handle more complex datasets and addressing emerging challenges.

Optimization research of handwritten digit recognition algorithm based on hardware neural networks

In the modern era of digitization, the widespread application of handwritten numerical data has led to an exponential increase in data volume, necessitating efficient real-time recognition and processing systems. This project is grounded in the foundational structure of neural networks, with a specific focus on integrating these networks into hardware through Very-Large-Scale Integration (VLSI). The primary objective is to achieve faster processing speeds, lower power consumption, and real-time operations. The central emphasis of this study is the design and implementation of a hardware neural network system tailored specifically for handwritten digit recognition. Drawing from neural network theory, we explore the construction of a hardware-based handwritten digit classifier. The fundamental model employed is the single-layer perceptron neuron model. Upon receiving 28x28 pixel grayscale images, the image classifier utilizes pre-trained weights, activation functions, and a maximum selector to compare and output recognition results for numerical digits. The concrete implementation is realized using the Verilog hardware description language, coupled with algorithm optimization strategies to enhance performance and efficiency. This research endeavor aims to provide an effective hardware solution for real-time handwritten digit recognition in the digital age.

Design and Simulation of Clock Divider using VHDL

This paper presents the diesign and simulation of clock divider circuit using VHDL(VHSIC Hardware Description Language) on an FPGA(Field Programmable Gate Array). The clock divider circuit is a fundamental component in digital system for generating lower frequency clocks from a higher frequency reference clock. The paper starts up with simple divider where the clock is divided by even numbers, odd numbers and then later expands it into non- integer dividers. Keywords:- clock divider, D flipflop, FPGA

AN EFFICIENT VLSI IMPLEMENTATION OF EDGE DETECTION OF IMAGES

Edge detection is a fundamental process in image processing with significant implications across multiple domains. Within the realm of object detection, the accurate delineation of image perimeters forms the bedrock for subsequent analysis. In this study, we present an optimized Laplacian Edge Detection algorithm tailored for efficient implementation in hardware.Leveraging approximation methodologies and strategic pipelining, we streamline complex operations, thereby reducing latency and resource consumption. Our implementation, realized through the Verilog Hardware Description Language (VHDL), stands as a testament to the efficacy of our approach. Through rigorous optimization and meticulous comparison with conventional Sobel edge detection, we demonstrate superior performance metrics, including enhanced Area utilization, reduced Time Delay, and improved Power Efficiency. This work underscores the importance of methodological refinement and technological innovation in advancing edge detection techniques for practical applications. Keywords: Laplacian, Sobel, Kernel, Pixel range, Area, Power

The Genesis of AIbyAI Integrated Circuit: Where AI Creates AI

The typical Integrated Circuit (IC) development process commences with formulating specifications in natural language and subsequently proceeds to Register Transfer Level (RTL) implementation. RTL code is traditionally generated through manual efforts, using Hardware Description Languages (HDL) such as VHDL or Verilog. High-Level Synthesis (HLS), on the other hand, converts programming languages to HDL; these methods aim to streamline the engineering process, minimizing human effort and errors. Currently, Electronic Design Automation (EDA) algorithms have been improved with the use of AI, with new advancements in commercial (such as ChatGPT, Bard, among others) Large Language Models (LLM) and open-source tools presenting an opportunity to automate the chip design process. This paper centers on the creation of AIbyAI, a Convolutional Neural Network (CNN) IC entirely developed by an LLM (ChatGPT-4), and its manufacturing with the first fabricable open-source Process Design Kit (PDK), SKY130A. The challenges, opportunities, advantages, disadvantages, conversation flow, and workflow involved in CNN IC development are presented in this work, culminating in the manufacturing process of AIbyAI using a 130 nm technology, marking a groundbreaking achievement as possibly the world’s first CNN entirely written by AI for its IC manufacturing with a free PDK, being a benchmark for systems that can be generated today with LLMs.

Design and Test of Offset Quadrature Phase-Shift Keying Modulator with GF180MCU Open Source Process Design Kit

This article explores the evolution of integrated circuits (ICs), highlighting the fundamental role of open source Electronic Design Automation (EDA) tools in their development. It describes the IC’s design flow, differentiating between Front-end and Back-end design stages, and details the process of implementing the digital stage in offset quadrature phase-shift keying (OQPSK) modulation in an IC, including its hardware description language (HDL), the implementation test in the field-programmable gate array (FPGA), and the physical layout using the first manufactured open source process design kits (PDKs) in Global Foundries’ 180 nm, as well as the use of OpenLane and Caravel. To conclude, the results of the physical tests obtained from the digital modulation are presented, as well as the performance of the raised cosine shaping filter.

A Versatile Approach for Adaptive Grid Mapping and Grid Flex-Graph Exploration with a Field-Programmable Gate Array-Based Robot Using Hardware Schemes.

Robotic exploration in dynamic and complex environments requires advanced adaptive mapping strategies to ensure accurate representation of the environments. This paper introduces an innovative grid flex-graph exploration (GFGE) algorithm designed for single-robot mapping. This hardware-scheme-based algorithm leverages a combination of quad-grid and graph structures to enhance the efficiency of both local and global mapping implemented on a field-programmable gate array (FPGA). This novel research work involved using sensor fusion to analyze a robot's behavior and flexibility in the presence of static and dynamic objects. A behavior-based grid construction algorithm was proposed for the construction of a quad-grid that represents the occupancy of frontier cells. The selection of the next exploration target in a graph-like structure was proposed using partial reconfiguration-based frontier-graph exploration approaches. The complete exploration method handles the data when updating the local map to optimize the redundant exploration of previously explored nodes. Together, the exploration handles the quadtree-like structure efficiently under dynamic and uncertain conditions with a parallel processing architecture. Integrating several algorithms into indoor robotics was a complex process, and a Xilinx-based partial reconfiguration approach was used to prevent computing difficulties when running many algorithms simultaneously. These algorithms were developed, simulated, and synthesized using the Verilog hardware description language on Zynq SoC. Experiments were carried out utilizing a robot based on a field-programmable gate array (FPGA), and the resource utilization and power consumption of the device were analyzed.

A Reconfigurable Hardware Realization for Real-Time Simulation of Cardiac Excitation and Conduction

Dynamic simulation of complex cardiac excitation and conduction requires high computational time. Thus, the hardware techniques that can run in real-time simulation were introduced. However, according to existing studies, the hardware simulation requires high power consumption and involves a large size of the physical parts. Due to the drawbacks, this research presents the adaptation of nonlinear Ordinary Differential Equation (ODE)-based cardiac excitable models of Luo-Rudy Phase I (LR-I) and FitzHugh-Nagumo (FHN) in a reconfigurable hardware of field-programmable gate array (FPGA). FPGA rapid prototyping using MATLAB Hardware Description Language (HDL) Coder was used to convert a fixed-point MATLAB Simulink blocks design of the cardiac models into a synthesizable VHSIC Hardware Description Language (VHDL) code and verified using the FPGA-In-the Loop (FIL) Co-simulator. The Xilinx FPGA Virtex-6 XC6VLX240T ML605 evaluation board was chosen as the FPGA platform. The cardiac excitation response characteristics using the LR-I model and the simulations of reentrant initiation and annihilation using the FHN model were verified in Virtex-6 FPGA. This means a new real-time simulation-based analysis technique of cardiac electrical excitation and conduction wassuccessfully developed using the reconfigurable hardware.

Hardware Acceleration of Digital Pulse Shape Analysis Using FPGAs.

The BC501A sensor is a liquid scintillator frequently used in nuclear physics for detecting fast neutrons. This paper describes a hardware implementation of digital pulse shape analysis (DPSA) for real-time analysis. DPSA is an algorithm that extracts the physically relevant parameters from the detected BC501A signals. The hardware solution is implemented in a MicroTCA system that provides the physical, mechanical, electrical, and cooling support for an AMC board (NAMC-ZYNQ-FMC) with a Xilinx ZYNQ Ultrascale-MP SoC. The Xilinx FPGA programmable logic implements a JESD204B interface to high-speed ADCs. The physical and datalink JESD204B layers are implemented using hardware description language (HDL), while the Xilinx high-level synthesis language (HLS) is used for the transport and application layers. The DPSA algorithm is a JESD204B application layer that includes a FIR filter and a constant fraction discriminator (CFD) function, a baseline calculation function, a peak detection function, and an energy calculation function. This architecture achieves an analysis mean time of less than 100 µs per signal with an FPGA resource utilization of about 50% of its most used resources. This paper presents a high-performance DPSA embedded system that interfaces with a 1 GS/s ADC and performs accurate calculations with relatively low latency.

FPGA-Based Speed Control Strategy of PMSM Using Improved Beetle Antennae Search Algorithm

To improve performance in terms of overshoot and motor response speed when a permanent-magnet synchronous motor (PMSM) with a proportional–integral (PI) controller is subjected to external disturbances, this paper proposes a speed control strategy based on an enhanced Beetle Antennae Search algorithm, which allows for adjustable parameters of the PI controller within a certain range. Firstly, to enhance the global and local search capabilities of each individual beetle, the step size was improved by linearly decreasing it. Secondly, a simulation model of a PMSM closed-loop control system was built to verify the effectiveness of the improved Beetle Antennae Search (BAS) algorithm. Finally, a linear feedback shift register model that generates four random numbers was developed on a field-programmable gate array (FPGA). The improved BAS algorithm for the PMSM control system was implemented on an FPGA using the Verilog hardware description language, and the feasibility of the system was verified through hardware simulation. Additionally, the hardware resource consumption on different FPGA platforms was analyzed. The simulation results demonstrate that the proposed new speed control strategy can reduce the overshoot and improve the motor response speed.

Leveraging CRC Error Detection for Enhanced Error Correction in Digital Communication Systems

In this study, CRC error detection techniques will be used to not only identify but fix single-bit errors in digital communication systems. In the past, CRC codes have been employed mainly for their ability to detect errors efficiently. However, this paper suggests a new way that will make it possible to modify CRC functions and thus correct the identified errors. It is intended that by using an optimized look-up table in Verilog hardware description language with an advanced Xilinx 14.7 toolchain, this research can increase the dependability and effectiveness of error correction mechanisms found in digital systems. The study presents how to create a detailed hardware description, optimize lookup tables for minimal resource usage and increased error correction capability; then synthesizes design with Xilinx 14.7.The conclusion makes a practical contribution towards identification and removal of single-bit errors which indicates a turning point in the use of Cyclic Redundancy Check (CRC) technology from being just about error detection to full scale error correction. This enhancement has the potential to greatly increase the durability and reliability of data transmission and storage systems, especially in critical applications requiring utmost data integrity. Keywords: Cyclic Redundancy Check (CRC), Error detection, Single-bit errors, Optimized lookup table, Xilinx 14.7 toolchain.

Development of mobile heart rate monitoring tools using artificial neural networks

Currently, there is a great need for mobile monitoring systems used to detect heart rate abnormalities in citizens working or living in hard-to-reach areas. Due to problems with transmitting data from such areas, it is desirable to carry out the entire information processing process at the study site. But, despite the limited hardware costs for the implementation of such systems, it is necessary to ensure high reliability of monitoring results. Purpose is to develop a structural diagram of a mobile heart rate analysis device, select the architecture of the neural network of the conversion and segmentation subsystem of the mobile device, determine the structure of the neural network of the conversion and segmentation subsystem, train the neural network of the conversion and segmentation subsystem, conduct software modeling of the neural network of the conversion and segmentation subsystem, implementation of a neural network conversion and segmentation subsystem based on field programmable gate arrays (FPGAs). A structural diagram of a mobile heart rate analysis device has been developed. The choice of the neural network architecture of the mobile device conversion and segmentation subsystem is justified. The structure of the neural network of the transformation and segmentation subsystem is determined. The neural network of the transformation and segmentation subsystem was trained. A software simulation of the neural network of the transformation and segmentation subsystem was carried out, confirming the high reliability of the proposed neural network structure. A neural network conversion and segmentation subsystem has been implemented in the hardware description language VHDL based on an FPGA. The developed structural diagram of the mobile device and the neural network structure of the conversion and segmentation subsystem can be used when implementing mobile heart rate monitoring means.

A Compact Model of Carbon Nanotube Field-Effect Transistors for Various Sizes with Bipolar Characteristics

Carbon nanotubes have excellent electrical properties and can be used as a new generation of semiconductor materials. This paper presents a compact model for carbon nanotube field-effect transistors (CNTFETs). The model uses a semi-empirical approach to model the current–voltage properties of CNTFETs with gate lengths exceeding 100 nm. This study introduces an innovative approach by proposing physical parametric reference lengths (Lref), which facilitate the integration of devices of varying sizes into a unified modeling framework. Furthermore, this paper develops models for the bipolar properties of carbon nanotube devices, employing two distinct sets of model parameters for enhanced accuracy. The model offers a comprehensive analysis of the different capacitances occurring between the electrodes within the device. The simulation of the model shows good agreement with the experimental measurements, confirming the model’s validity. The model is implemented in the Verilog-A hardware description language, with the circuit being subsequently constructed and subjected to simulations via the HSPICE tool. The CNTFET-based inverter exhibits a gain of 7.022 and a delay time of 16.23 ps when operated at a voltage of 1.2 V.

Efficient Hardware Accelerator and Implementation of JPEG 2000 MQ Decoder Architecture

Due to the extensive use of multimedia technologies, there is a pressing need for advancements and enhanced efficiency in picture compression. JPEG 2000 standard aims to meet the needs for encoding still pictures. JPEG 2000 is an internationally recognized standard for compressing still images. It provides a wide range of features and offers superior compression ratios and interesting possibilities when compared to traditional JPEG approaches. Nevertheless, the MQ decoder in the JPEG 2000 standard presents a substantial obstacle for real-time applications. In order to fulfill the demands of real-time processing, it is imperative to meticulously devise a high-speed MQ decoder architecture. This work presents a novel MQ decoder architecture that is both high-speed and area-efficient, making it comparable to previous designs and well-suited for chip implementation. The design is implemented using the VHDL hardware description language and is synthesized with Xilinx ISE 14.7 and Vivado 2015.1. The implementation findings show that the design functions at a frequency of 438.5 MHz on Virtex-6 and 757.5 MHz on Zync7000. For these particular frequencies, the calculated frame rate is 63.1 frames per second.

High-Matching and Low-Cost Realization of the FHN Neuron Model on Reconfigurable FPGA Board.

The main objectives of neuromorphic engineering are the research, modeling, and implementation of neural functioning in the human brain. We provide a hardware solution that can replicate such a nature-inspired system by merging multiple scientific domains and is based on neural cell processes. This work provides a modified version of the original Fitz-Hugh Nagumo (FHN) neuron using a simple 2V term called Hybrid Piece-Wised Base-2 Model (HPWBM), which accurately reproduces numerous patterns of the original neuron model. With reduced terms, we suggest modifying the original nonlinear term to achieve high matching accuracy and little computing error. Time domain and phase portraits are used to validate the proposed model, which shows that it can reproduce all of the FHN model's properties with high accuracy and little mistake. We provide an effective digital hardware approach for large-scale neuron implementations based on resource-sharing and pipelining strategies. The Hardware Description Language (HDL) is used to construct the hardware on an FPGA as a proof of concept. The recommended model hardly uses 0.48 percent of the resources on a Virtex 4 FPGA board, according to the results of the hardware implementation. The circuit can run at a maximum frequency of 448.236 MHz, according to the static timing study.

Design and Implementation of SRAM Using Verilog

Abstract: This comprehensive review delves into the intricate realm of the Static Random-Access Memory (SRAM) design and implementation, elucidating its pivotal role in shaping the performance, efficiency, and reliability of contemporary electronic systems, involving applications in ASIC devices. With a primary focus on the integration of Verilog, a hardware description language (HDL), the paper provides an in-depth background on SRAM, meticulously detailing its architecture, operation, and overall significance in electronic systems. The review meticulously addresses challenges inherent in SRAM design, encompassing considerations such as power consumption, speed, and area efficiency. Significantly, it underscores the crucial role of Verilog by delving into its syntax, modules, and procedural constructs, showcasing its application in modeling key SRAM components. The discussion extends to design trade-offs, including size, speed, and power consumption, illustrating how Verilog plays a pivotal role in facilitating optimal parameter optimization. The review seamlessly integrates technical concepts like RTL (Register Transfer Level), and procedural assignments, ensuring a comprehensive exploration of SRAM design intricacies. Additionally, it introduces terms such as testbench, bitcell and power reduction, further enhancing the reader's understanding of the complex interplay between Verilog and SRAM design.

Radar-Jamming Decision-Making Based on Improved Q-Learning and FPGA Hardware Implementation

In contemporary warfare, radar countermeasures have become multifunctional and intelligent, rendering the conventional jamming method and platform unsuitable for the modern radar countermeasures battlefield due to their limited efficiency. Reinforcement learning has been proven to be a practical solution for cognitive jamming decision-making in the cognitive electronic warfare. In this paper, we proposed a radar-jamming decision-making algorithm based on an improved Q-Learning algorithm. This improved Q-Learning algorithm ameliorated the problem of overestimating the Q-value that exists in the Q-Learning algorithm by introducing a second Q-table. At the same time, we performed a comprehensive design and implementation based on the classical Q-Learning algorithm, deploying it to a Field Programmable Gate Array (FPGA) hardware. We decomposed the implementation of the reinforcement learning algorithm into individual steps and described each step using a hardware description language. Then, the reinforcement learning algorithm can be computed on FPGA by linking the logic modules with valid signals. Experiments show that the proposed Q-Learning algorithm obtains considerable improvement in performance over the classical Q-Learning algorithm. Additionally, they confirm that the FPGA hardware can achieve great efficiency improvement on the radar-jamming decision-making algorithm implementation.