Hardware Description Language Code Research Articles

Development of field programmable gate array–based encryption module to mitigate man-in-the-middle attack for nuclear power plant data communication network

This article presents a security module based on a field programmable gate array (FPGA) to mitigate man-in-the-middle cyber attacks. Nowadays, the FPGA is considered to be the state of the art in nuclear power plants I&C systems due to its flexibility, reconfigurability, and maintainability of the FPGA technology; it also provides acceptable solutions for embedded computing applications that require cybersecurity. The proposed FPGA-based security module is developed to mitigate information-gathering attacks, which can be made by gaining physical access to the network, e.g., a man-in-the-middle attack, using a cryptographic process to ensure data confidentiality and integrity and prevent injecting malware or malicious data into the critical digital assets of a nuclear power plant data communication system. A model-based system engineering approach is applied. System requirements analysis and enhanced function flow block diagrams are created and simulated using CORE9 to compare the performance of the current and developed systems. Hardware description language code for encryption and serial communication is developed using Vivado Design Suite 2017.2 as a programming tool to run the system synthesis and implementation for performance simulation and design verification. Simple windows are developed using Java for physical testing and communication between a personal computer and the FPGA.

Hardware implementation of auto-mutual information function for condition monitoring

This study is aimed at showing the applicability of mutual information, namely auto-mutual information function for condition monitoring in electrical motors, through age detection in accelerated motor aging. Vibration data collected in artificial induction motor experiment is used for verification of both the original auto-mutual information function algorithm and its hardware implementation in Verilog, produced from an initial version made with MATLAB HDL (Hardware Description Language) Coder. A conceptual model for industry and education based on a field programmable logic array development board is developed and demonstrated on the auto-mutual information function example while suggesting other applications as well. It has also been shown that attractor reconstruction for the vibration data cannot be straightforward.

FPGA Implementation of Sensorless Sliding Mode Observer With a Novel Rotation Direction Detection for PMSM Drives

This paper proposes an field programmable gate array (FPGA) implementation of a sensorless controller for surface mounted permanent magnet synchronous machines. Position and speed are both estimated by a sliding mode observer (SMO) which is based on the PMSM stator frame model. The sliding mode manifold is chosen on the real stator current trajetory. In the SMO, a sign function of current error in the feedback correction is adopted. The estimated speed and position are realized on an FPGA controller by COordinate Rotation Digital Computer (CORDIC) algorithm. Using model-based design, with the tools of MATLAB/Simulink and hardware description language coder, the whole control system is designed and implemented in a single FPGA chip. Dedicated hardware optimization algorithms such as pipeline and resource sharing are developed for the implementation as well. The sign function is realized by fully hardware with a relatively high switching frequency. Meanwhile, a fast and practical rotation direction detection method which is based on back electromotive force information is proposed. Experimental results show that the proposed FPGA implemented sensorless SMO for PMSM drives is robust and has high performance.

Xilinx Spartan 3A DSP FPGA based DC Voltage Regulators for PV Systems

This paper explains the design and implementation of Perturb and Observe Maximum Power Point Tracking Algorithm combined with the Closed Loop Digital PI control algorithm to generate the Digital Pulse Width Modulation using Xilinx Spartan 3A DSP Field Programmable Gate Array for regulating the load voltage of DC-DC buck converter. And also concentrates on the methods for generation of DPWM techniques say Delay line based Digital Pulse Width Modulation and Hybrid based Digital Pulse Width Modulation with the 210 bit resolution. All the algorithms are developed by VHSIC Hardware Description Language coding and are implemented using Xilinx ISE 12.1 tool. The hardware results validate the satisfactory voltage regulation of PV system under continuous changing weather condition. The Hybrid based Digital Pulse Width Modulation seems to have better time transient response than the Delay line based Digital Pulse Width Modulation.

A software framework for pipelined arithmetic algorithms in field programmable gate arrays

Pipelined algorithms implemented in field programmable gate arrays are extensively used for hardware triggers in the modern experimental high energy physics field and the complexity of such algorithms increases rapidly. For development of such hardware triggers, algorithms are developed in C++, ported to hardware description language for synthesizing firmware, and then ported back to C++ for simulating the firmware response down to the single bit level. We present a C++ software framework which automatically simulates and generates hardware description language code for pipelined arithmetic algorithms.

Data Secrecy Protection Through Information Flow Tracking in Proof-Carrying Hardware IP—Part I: Framework Fundamentals

Proof-carrying hardware intellectual property (PCHIP) is a previously proposed framework for ensuring trustworthiness of third-party hardware IP through the development of formal proofs for security properties designed to prevent introduction of malicious behavior. Based on this framework, we introduce new approaches for assuring that the secrecy of internal information in a hardware design is not compromised by design flaws or malicious hardware Trojans. Specifically, we devise two PCHIP-based information flow tracking approaches, which enhance the formal PCHIP framework with secrecy tags and/or sensitivity levels in order to provide mechanisms for proving that sensitive information does not reach undesired sites. To assist in the development of data secrecy properties, we also introduce the concept of theorem generation functions, which enable generation of security theorems independent of the target circuit, thereby paving the way for proof automation. In addition, we enhance the PCHIP framework with a hierarchy-preserving methodology and we show its utility in preventing malicious data modification, which may indirectly result in sensitive information leakage, such as by modifying the secret key in a cryptographic core. This enhanced PCHIP framework also enables development of hybrid module libraries, which contain hardware description language code along with proofs of lemmas for these modules. These module libraries can then be used for hierarchically proving security properties in higher level designs, thereby reducing the proof development burden in the general PCHIP framework. Efforts toward automation of the proposed methodologies, as well as evaluation of their effectiveness in identifying design flaws or hardware Trojans in various cryptographic hardware designs are presented in part II of this paper series.

Performance Evaluation of Verilog Coding Techniques for Optimized MD5 Algorithm

Nowadays all electronic devices focus on high performance implementation. One of the well-known methods to represent the concept of hardware implementation is HDL design style, where Verilog HDL and VHDL are widely used as Hardware Description Language (HDL). These HDLs are portable and technology-independent. Verilog HDL code focuses on bottom-up system design while VHDL focuses on top-down design. Efficient coding can cause better performance but bad coding may degrade performance even if the system is successfully designed. This paper discusses the performance analysis of MD5 design in term of frequency maximum, logic utilization and power analysis for both MD5 design with and without controller. FPGAs provide flexibility for their re-configurability and low cost. Therefore, FPGAs are suitable to implement various design implementation caused by different coding styles. In this paper, MD5 algorithms are designed using Verilog, then synthesized and simulated using Altera Quartus II and ModelSim. The maximum frequency of MD5 design improve significantly with 135.78 MHz. The total register is 586 and combinational ALUT is 712. Besides, the power of the MD5 design is analyzed by filtering the glitch in the power analysis section. Thus, Verilog HDL Coding Style and Altera Quartus II play an important role in designing high-performance design.

Sensor Fault Detection and Isolation Based on Artificial Neural Networks and Fuzzy Logic Applicated on Induction Motor for Electrical Vehicle

<p>Recently, research has picked up a fervent pace in the area of fault diagnosis of electrical vehicle. Like failures of a position sensor, a voltage sensor, and current sensors. Three-phase induction motors are the “workhorses” of industry and are the most widely used electrical machines. This paper presents a scheme for Fault Detection and Isolation (FDI). The proposed approach is a sensor-based technique using the mains current measurement. Current sensors are widespread in power converters control and in electrical drives. Thus, to ensure continuous operation with reconfiguration control, a fast sensor fault detection and isolation is required. In this paper, a new and fast faulty current sensor detection and isolation is presented. It is derived from intelligent techniques. The main interest of field programmable gate array is the extremely fast computation capabilities. That allows a fast residual generation when a sensor fault occurs. Using of Xilinx System Generator in Matlab / Simulink allows the real-time simulation and implemented on a field programmable gate array chip without any VHSIC Hardware Description Language coding. The sensor fault detection and isolation algorithm was implemented targeting a Virtex5. Simulation results are given to demonstrate the efficiency of this FDI approach.</p>

Design verification enhancement of field programmable gate array-based safety-critical I&C system of nuclear power plant

Safety-critical instrumentation and control (I&C) system in nuclear power plant (NPP) implemented on programmable logic controllers (PLCs) plays a vital role in safe operation of the plant. The challenges such as fast obsolescence, the vulnerability to cyber-attack, and other related issues of software systems have currently led to the consideration of field programmable gate arrays (FPGAs) as an alternative to PLCs because of their advantages and hardware related benefits. However, safety analysis for FPGA-based I&C systems, and verification and validation (V&V) assessments still remain important issues to be resolved, which are now become a global research point of interests. In this work, we proposed a systematic design and verification strategies from start to ready-to-use in form of model-based approaches for FPGA-based reactor protection system (RPS) that can lead to the enhancement of the design verification and validation processes. The proposed methodology stages are requirement analysis, enhanced functional flow block diagram (EFFBD) models, finite state machine with data path (FSMD) models, hardware description language (HDL) code development, and design verifications. The design verification stage includes unit test – Very high speed integrated circuit Hardware Description Language (VHDL) test and modified condition decision coverage (MC/DC) test, module test – MATLAB/Simulink Co-simulation test, and integration test – FPGA hardware test beds. To prove the adequacy of the proposed approaches, the design architect that focused on the RPS bistable trip logics which are the safety-critical functions of RPS are designed, analyzed, verified and discussed, using bistable fixed setpoint trip logic algorithms as case study. The results showed that the proposed approaches can enhance the design verification processes alongside the reduction in rigorous V&V tasks of FPGA-based safety-critical I&C system for NPP.

An Intelligent Vehicular Traffic Signal Control System with State Flow Chart Design and FPGA Prototyping

The problem of vehicular traffic congestion is a persistent constraint in the socio-economic development of Pakistan. This paper presents design and implementation of an intelligent traffic controller based on FPGA (Field Programmable Gate Array) to provide an efficient traffic management by optimizing functioning of traffic lights which will result in minimizing traffic congestion at intersections. The existent Traffic Signal system in Pakistan is fixed-time based and offers only Open Loop method for Traffic Control. The Intelligent Traffic Controller presented here uses feedback sensors to read the Traffic density present at a four way intersection to provide an efficient alternative for better supervisory Control of Traffic flow. The traffic density based control logic has been developed in a State Flow Chart for improved visualization of State Machine based operation, and implemented as a Subsystem in Simulink and transferred into VHDL (Hardware Description Language) code using HDL Coder for reducing development time and time to market, which are essential to capitalize Embedded Systems Market. The VHDL code is synthesized with Altera QUARTUS, simulated timing waveform is obtained to verify correctness of the algorithm for different Traffic Scenarios. For implementation purpose estimations were obtained for Cyclone-III and Stratix-III.

Software-Defined Radio FPGA Cores: Building towards a Domain-Specific Language

This paper reports on the design and implementation of an open-source library of parameterizable and reusable Hardware Description Language (HDL) Intellectual Property (IP) cores designed for the development of Software-Defined Radio (SDR) applications that are deployed on FPGA-based reconfigurable computing platforms. The library comprises a set of cores that were chosen, together with their parameters and interfacing schemas, based on recommendations from industry and academic SDR experts. The operation of the SDR cores is first validated and then benchmarked against two other cores libraries of a similar type to show that our cores do not take much more logic elements than existing cores and that they support a comparable maximum clock speed. Finally, we propose our design for a Domain-Specific Language (DSL) and supporting tool-flow, which we are in the process of building using our SDR library and the Delite DSL framework. We intend to take this DSL and supporting framework further to provide a rapid prototyping system for SDR application development to programmers not experienced in HDL coding. We conclude with a summary of the main characteristics of our SDR library and reflect on how our DSL tool-flow could assist other developers working in SDR field.

Improved Data Preprocessing Algorithm for Time-Domain Induced Polarization Method with Digital Notch Filter

Time-domain induced polarization (TDIP) measurement is seriously affected by power line interference and other field noise. Moreover, existing TDIP instruments generally output only the apparent chargeability, without providing complete secondary field information. To increase the robustness of TDIP method against interference and obtain more detailed secondary field information, an improved data-processing algorithm is proposed here. This method includes an efficient digital notch filter which can effectively eliminate all the main components of the power line interference. Hardware model of this filter was constructed and Vhsic Hardware Description Language code for it was generated using Digital Signal Processor Builder. In addition, a time-location method was proposed to extract secondary field information in case of unexpected data loss or failure of the synchronous technologies. Finally, the validity and accuracy of the method and the notch filter were verified by using the Cole-Cole model implemented by Simulink software. Moreover, indoor and field tests confirmed the application effect of the algorithm in the fieldwork.

Design and Co-Simulation of Depth Estimation Using Simulink HDL Coder and Modelsim

In this paper a novel VHDL design procedure of depth estimation algorithm using HDL (Hardware Description Language) Coder is presented. A framework is developed that takes depth estimation algorithm described in MATLAB as input and generates VHDL code, which dramatically decreases the time required to implement an application on FPGAs (Field Programmable Gate Arrays). In the first phase, design is carriedout in MATLAB. Using HDL Coder, MATLAB floating- point design is converted to an efficient fixed-point design and generated VHDL Code and test-bench from fixed point MATLAB code. Further, the generated VHDL code of design is verified with co-simulation using Mentor Graphic ModelSim10.3d software. Simulation results are presented which indicate that VHDL simulations match with the MATLAB simulations and confirm the efficiency of presented methodology.

Automated Metabolic P System Placement in FPGA

Abstract An original Very High Speed Integrated Circuit Hardware Description Language (VHDL) code generation tool that can be used to automate Metabolic P (MP) system implementation in hardware such as Field Programmable Gate Arrays (FPGA) is described. Unlike P systems, MP systems use a single membrane in their computations. Nevertheless, there are many biological processes that have been successfully modeled by MP systems in software. This is the first attempt to analyze MP system hardware implementations. Two different MP systems are investigated with the purpose of verifying the developed software: the model of glucose–insulin interactions in the Intravenous Glucose Tolerance Test (IVGTT), and the Non-Photochemical Quenching process. The implemented systems’ calculation accuracy and hardware resource usage are examined. It is found that code generation tool works adequately; however, a final decision has to be done by the developer because sometimes several implementation architecture alternatives have to be considered. As an archetypical example serves the IVGTT MP systems’ 21–23 bits FPGA implementation manifesting this in the Digital Signal Processor (DSP), slice, and 4-input LUT usage.

A high performance cost-effective digital complex correlator for an X-band polarimetry survey.

The detailed knowledge of the Milky Way radio emission is important to characterize galactic foregrounds masking extragalactic and cosmological signals. The update of the global sky models describing radio emissions over a very large spectral band requires high sensitivity experiments capable of observing large sky areas with long integration times. Here, we present the design of a new 10 GHz (X-band) polarimeter digital back-end to map the polarization components of the galactic synchrotron radiation field of the Northern Hemisphere sky. The design follows the digital processing trends in radio astronomy and implements a large bandwidth (1 GHz) digital complex cross-correlator to extract the Stokes parameters of the incoming synchrotron radiation field. The hardware constraints cover the implemented VLSI hardware description language code and the preliminary results. The implementation is based on the simultaneous digitized acquisition of the Cartesian components of the two linear receiver polarization channels. The design strategy involves a double data rate acquisition of the ADC interleaved parallel bus, and field programmable gate array device programming at the register transfer mode. The digital core of the back-end is capable of processing 32 Gbps and is built around an Altera field programmable gate array clocked at 250 MHz, 1 GSps analog to digital converters and a clock generator. The control of the field programmable gate array internal signal delays and a convenient use of its phase locked loops provide the timing requirements to achieve the target bandwidths and sensitivity. This solution is convenient for radio astronomy experiments requiring large bandwidth, high functionality, high volume availability and low cost. Of particular interest, this correlator was developed for the Galactic Emission Mapping project and is suitable for large sky area polarization continuum surveys. The solutions may also be adapted to be used at signal processing subsystem levels for large projects like the square kilometer array testbeds.

Hardware-in-the-Loop Emulation of Linear Induction Motor Drive for MagLev Application

Linear induction machines are widely used in transportation systems due to their many advantages. Design and prototyping of electric machines are an expensive and time-consuming process; hardware-in-the-loop simulation provides an efficient alternative. In this paper, a field-programmable gate array-based real-time digital emulation of single-sided linear induction motor with the drive system is proposed. Implementation of the model is performed in both fixed-point using Xilinx system generator and floating-point number representations using a handwritten VHSIC Hardware Description Language code. Then, an evaluation in terms of real-time step-size and accuracy as well as hardware resource utilization is provided. The whole design was fully paralleled, which resulted in a considerable reduction of model execution time. The minimum time step of 2.3 and 0.8 $\mu \text{s}$ was achieved for floating-point and fixed-point implementations, respectively. The results of the real-time simulation are verified by the experimental results as well as a 2-D finite-element simulation in JMAG software.

Optimization in MATLAB for Cardiac Excitation Modeling towards FPGA Standalone Simulation Tools

In past few decades, most of the modern electrophysiological concepts and methods were developed by the computational technique extensively to compute the cardiac action potential in nerve cells. Thus, tissue models consisting of a large number of single cell models cause a problem in the amount of computation required to obtain meaningful results from simulations. One of the solutions to this problem is by implementing the simulation through hardware modeling using a Field Programmable Gate Array (FPGA). Here, a research on developing a real-time simulation tool responsible for reentrant excitations in a ring of cardiac tissue based on the FitzHugh-Nagumo (FHN) model has been carried out by using a Xilinx Virtex-6 XC6VLX240T ML605 development board FPGA. In order to invest some of the time savings for creating the FPGA prototype, rapid prototyping method introduced by MathWorks which are MATLAB Simulink and its HDL Coder toolbox have been used to automate the algorithm design process by converting Simulink blocks into Hardware Description Language (HDL) code for the FPGA using a fixed-point data type in discrete-time framework. In this paper, the method and the optimization of the HDL design through the MATLAB Simulink have been discussed and the FPGA hardware performance in terms of speed, area and power consumption has also been analyzed.

Development of gamma spectroscopy employing NaI(Tl) detector 3 inch × 3 inch and readout electronic of flash-ADC/FPGA-based technology

Abstract In this article the development of a gamma spectroscopy system is described using a scintillation detector NaI(Tl) of 3 inch × 3 inch. The readout electronic for the spectroscopy is built from the fast analog-digital conversion of Flash Analog-Digital Converter (Flash-ADC) 250 MHz – 8 bits resolution, and the embedded Field-Programmable Gate Array (FPGA) technology. The embedded VHSIC Hardware Description Language (VHDL) code for FPGA is built in such a way that it works as a multi channel analyser (MCA) with 4096 Digital Charge Integration (DCI) channels. A pulse generator with frequency varying from Hz up to 12 kHz is used to evaluate the time response of the system. Two standard radioisotope sources of 133Ba and 152Eu with multi gamma energies ranging from several tens keV to MeV are used to evaluate the linearity and energy resolution of the system.

Implementation of High Performance Electronic Circuits for Zero Suppression and Encoding of Digital Signals

This paper presents a design of a data processing circuit for receiving digital signals from front end-electronic board chips of a specific nuclear detector, encoding and triggering them via specific optical links operating at a specific frequency. Such processed signals are then fed to a data acquisition system (DAQ) for analysis. Very high-speed integrated circuit hardware description language (VHDL) algorithms and codes were created to implement this design using field programmable gate array (FPGA) devices. The obtained data were simulated using international standard simulators.

Building Information Modeling using Hardware Genetic Algorithms with Field-Programmable Gate Arrays

Genetic algorithms (GAs) have found many applications in various fields such as physics, signal processing, artificial intelligence and recently construction engineering management. For a long time, GAs are usually criticized to be time-consuming, making it unpractical for real-time applications. This paper presents a new technique which can be used: (1) to automate construction activities, and (2) to improve building information modeling which has become an attractive research topic around the world. Different from the generic GA techniques employed in the literature, this paper proposes a new GA using hardware with field-programmable gate arrays. The proposed technique is shown to improve speed and lessen computational power. Hardware implementation of GA using static random access memory-based field-programmable gate arrays with synthesizable very hardware description language coding is introduced. Detailed analyses on the field-programmable gate arrays are given which show that it is suitable for real-time applications. As a result, GA is modified so that it can be implemented in series and parallel which can greatly improve computational hardware performance. Configuration of parallelization is available with a peripheral component interconnect interface, which further helps to form a fast optimization tool for real-time applications. The ultimate goal of this paper is thus to design an effective GA technique which can be employed to support building information modeling and to effectively automate critical processes in construction projects.