Performance Evaluation of Verilog Coding Techniques for Optimized MD5 Algorithm

Abstract

Nowadays all electronic devices focus on high performance implementation. One of the well-known methods to represent the concept of hardware implementation is HDL design style, where Verilog HDL and VHDL are widely used as Hardware Description Language (HDL). These HDLs are portable and technology-independent. Verilog HDL code focuses on bottom-up system design while VHDL focuses on top-down design. Efficient coding can cause better performance but bad coding may degrade performance even if the system is successfully designed. This paper discusses the performance analysis of MD5 design in term of frequency maximum, logic utilization and power analysis for both MD5 design with and without controller. FPGAs provide flexibility for their re-configurability and low cost. Therefore, FPGAs are suitable to implement various design implementation caused by different coding styles. In this paper, MD5 algorithms are designed using Verilog, then synthesized and simulated using Altera Quartus II and ModelSim. The maximum frequency of MD5 design improve significantly with 135.78 MHz. The total register is 586 and combinational ALUT is 712. Besides, the power of the MD5 design is analyzed by filtering the glitch in the power analysis section. Thus, Verilog HDL Coding Style and Altera Quartus II play an important role in designing high-performance design.