Hardware Complexity Research Articles

Design of a Scan Chain for Side Channel Attacks on AES Cryptosystem for Improved Security

Scan chain-based attacks are side-channel attacks focusing on one of the most significant features of hardware test circuitry. A technique called Design for Testability (DfT) involves integrating certain testability components into a hardware design. However, this creates a side channel for cryptanalysis, providing crypto devices vulnerable to scan-based attacks. Advanced Encryption Standard (AES) has been proven as the most powerful and secure symmetric encryption algorithm announced by USA Government and it outperforms all other existing cryptographic algorithms. Furthermore, the on-chip implementation of private key algorithms like AES has faced scan-based side-channel attacks. With the aim of protecting the data for secure communication, a new hybrid pipelined AES algorithm with enhanced security features is implemented. This paper proposes testing an AES core with unpredictable response compaction and bit level-masking throughout the scan chain process. A bit-level scan flipflop focused on masking as a scan protection solution for secure testing. The experimental results show that the best security is provided by the randomized addition of masked scan flipflop through the scan chain and also provides minimal design difficulty and power expansion overhead with some negligible delay measures. Thus, the proposed technique outperforms the state-of-the-art LUT-based S-box and the composite sub-byte transformation model regarding throughput rate 2 times and 15 times respectively. And security measured in the avalanche effect for the sub-pipelined model has been increased up to 95 per cent with reduced computational complexity. Also, the proposed sub-pipelined S-box utilizing a composite field arithmetic scheme achieves 7 per cent area effectiveness and 2.5 times the hardware complexity compared to the LUT-based model.

Nadifit: a novel single position pulse based diagnostic system

Both traditional Chinese medicine (TCM) and traditional ayurvedic medicine (TAM) rely on a system of radial pulse diagnostics to assess a patient's health. The doctor or practitioner should place all three fingers on the patient's wrist and feel the styloid processes to detect any changes in the radial pulse. However, finding medical professionals skilled in pulse diagnosis or nadipariksha is becoming increasingly challenging in the current and upcoming generation. One technological approach that could solve this issue once and for all would be to transform objective pulse diagnosis into a subjective process. To automate this procedure, however, three separate sensors must be constructed for three positions in order to capture pulse at varying pulse pressures, which increases the hardware complexity for consumer use. To simplify the process and ensure a correct diagnosis, this study presents an effort to create the smart portable system Nadifit, which takes a single pulse reading from the patient. A single pulse is all that's needed to identify distinctive organ patterns, which can then be analyzed to provide insight into potential health issues. Analogue signals are quantified with the help of a microphone, a transmitter, and a 32-bit microprocessor. The data is acquired with a precision of 10 bits and virtually no electronic or contaminating noise outside of the system. The computer receives the collected pulse signal and does time and frequency domain analysis of the Nadi patterns, shapes, and width to determine the presence of the three ayurveda doshas (Vata, pitta, and kapha) as well as Chinese organ patterns (such as Qi stagnation, yin deficiency, yang excess, etc.). The experimental results demonstrate the effectiveness of the suggested system in identifying dosha, making it highly tailored to the individual patient's health issue. It is also demonstrated that the pulse waveform demonstrates the desired fluctuations in relation to patient age, pressure applied to the sensing element and full vs. empty stomach. Comparisons of stiffness across age groups are also performed. Practitioners, vaidhyas, and medical professionals are used to verify the system's accuracy. Hence, we believe a larger segment of the general public will be able to make use of our technology.

An Area-Efficient Unified VLSI Architecture for Type IV DCT/DST Having an Efficient Hardware Security with Low Overheads

This paper introduces an efficient solution for designing a unified VLSI implementation for type IV DCT/DST while solving one challenging problem in obtaining high performance VLSI chips for common goods, which is solving the security of the hardware while obtaining a VLSI implementation with high performance. The new solution uses a new systolic array algorithm for type IV DST that can allow us to obtain an efficient unified VLSI architecture with one previously designed for type IV DCT. The proposed method uses special arithmetic structures that have been called quasi-cycle convolutions that can be efficiently mapped on linear systolic arrays. Moreover, the obtained unified VLSI architecture, besides being an efficient implementation with a low hardware complexity and high-speed performance, allows for an efficient inclusion of the obfuscation technique with very low overheads.

Optical link encoding based simultaneous correction for crosstalk and nonlinearity in multi-site optical converged networks.

This paper reports a correction scheme to address the problem of modulation nonlinearity and optical switch crosstalk simultaneously for the multi-site optical converged network. Based on the optical link encoding and exclusive-or operation for the received signal, the present spectrum usage can be obtained among the confusion with interferences containing the modulated harmonic distortion and the crosstalk leakage from other sites. The proof-of-concept experiment is performed on various interferences involving the linear frequency modulated (LFM) waveform and the quadrature amplitude modulation (QAM) signal. The corrected spectrum has realized an improved signal-to-noise ratio (SNR) of over 22 dB compared to the uncorrected counterpart. Furthermore, it consistently maintains a superior SNR, surpassing the single impairment-corrected scenario by an impressive margin of at least 15.9 dB. Besides, the implementation would not introduce additional noise, making the corrected result agree well with the ideal case. Without any increase in hardware complexity, the presented scheme provides an effective technique to meet the correction challenge of large-scale and complicated optical networks with multiple optoelectronic devices.

Radix-64 Floating-Point Division and Square Root: Iterative and Pipelined Units

Digit-recurrence algorithms are widely used in actual microprocessors to compute floating-point division and square root. These iterative algorithms present a good trade-off in terms of performance, area and power. Traditionally, commercial processors have iterative division and square root units where the iteration logic is used over several cycles. The main drawbacks of these iterative units are long latency and low throughput due to the reuse of part of the logic over several cycles, and its hardware complexity with separated logic for division and square root. We present a radix-64 floating-point division and square root algorithm with a common iteration for division and square root and where, to have an affordable implementation, each radix-64 iteration is made of two simpler radix-8 iterations. The radix-64 algorithm allows to get low-latency operations, and the common division and square root radix-64 iteration results in some area reduction. The algorithm is mapped into two different microarchitectures: a low-latency and low area iterative unit, and a low-latency and high-throughput pipelined unit. In both units speculation between consecutive radix-8 iterations is used to reduce the timing.

Beam-Space MIMO Radar for Joint Communication and Sensing With OTFS Modulation

Motivated by automotive applications, we consider joint radar sensing and data communication for a system operating at millimeter wave (mmWave) frequency bands, where a Base Station (BS) is equipped with a co-located radar receiver and sends data using the Orthogonal Time Frequency Space (OTFS) modulation format. We consider two distinct modes of operation. In <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Discovery</i> mode, a single common data stream is broadcast over a wide angular sector. The radar receiver must detect the presence of not yet acquired targets and perform coarse estimation of their parameters (angle of arrival, range, and velocity). In <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Tracking</i> mode, the BS transmits multiple individual data streams to already acquired users via beamforming, while the radar receiver performs accurate estimation of the aforementioned parameters. Due to hardware complexity and power consumption constraints, we consider a hybrid digital-analog architecture where the number of RF chains and A/D converters is significantly smaller than the number of antenna array elements. In this case, a direct application of the conventional MIMO radar approach is not possible. Consequently, we advocate a <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">beam-space approach</i> where the vector observation at the radar receiver is obtained through a RF-domain beamforming matrix operating the dimensionality reduction from antennas to RF chains. Under this setup, we propose a likelihood function-based scheme to perform joint target detection and parameter estimation in Discovery, and high-resolution parameter estimation in Tracking mode, respectively. Our numerical results demonstrate that the proposed approach is able to reliably detect multiple targets while closely approaching the Cramér-Rao Lower Bound (CRLB) of the corresponding parameter estimation problem.

Energy-efficient design techniques for LUT based adaptive digital pre-distorters

Energy-efficient design techniques for an adaptive Look-Up Table (LUT) based Digital Predistortion (DPD) system are presented. The proposed methods are simplification of the adaptation function, reduction of the memory hardware complexity and bypassing of the equalizer circuit. The equalizer circuit block is critical while the adaptation loop is enabled but need for this block while the loop is disabled is explored to reduce power dissipation. Three adaptation functions that require less complex hardware are presented. The system is modeled with Matlab-Simulink, then implemented using an FPGA and 130 nm ST-Silicon On Insulator (SOI) process. More than 33% of power saving is obtained by applying the proposed techniques and further power reductions are also possible by configuring the system.

DL-PC algorithm for partially-connected hybrid precoding in massive MIMO systems

In hybrid precoding, a partially-connected (PC) architecture has aroused significant attention for its low hardware complexity. Unfortunately, the hybrid precoding with the PC architecture may suffer from a severe spectral efficiency loss. To overcome the loss, a deep learning-based hybrid precoding algorithm for the PC architecture is proposed in this paper. Firstly, the optimization problem of hybrid precoding is transformed into a neural network prediction problem. Furthermore, a convolutional neural network(CNN) is designed to predict the hybrid precoder, where the channel matrix is used as input. Especially, to meet the constraints of the hybrid precoder, two lambda layers are introduced into the CNN architecture. Specifically, a lambda1 layer is constructed to address the constant modulus constraint of the analog precoding matrix and the block diagonal constraint. Then, a lambda2 layer is constructed to optimize the digital precoding matrix and address the transmit power constraint. Finally, the vectorized hybrid precoding matrix is output by the well-trained network. Simulation results show that the proposed algorithm can enhance spectral efficiency and energy efficiency with lower computation time.

A quantum-inspired probabilistic prime factorization based on virtually connected Boltzmann machine and probabilistic annealing

Probabilistic computing has been introduced to operate functional networks using a probabilistic bit (p-bit), broadening the computational abilities in non-deterministic polynomial searching operations. However, previous developments have focused on emulating the operation of quantum computers similarly, implementing every p-bit with large weight-sum matrix multiplication blocks and requiring tens of times more p-bits than semiprime bits. In addition, operations based on a conventional simulated annealing scheme required a large number of sampling operations, which deteriorated the performance of the Ising machines. Here we introduce a prime factorization machine with a virtually connected Boltzmann machine and probabilistic annealing method, which are designed to reduce the hardware complexity and number of sampling operations. From 10-bit to 64-bit prime factorizations were performed, and the machine offers up to 1.2 × 108 times improvement in the number of sampling operations compared with previous factorization machines, with a 22-fold smaller hardware resource.

Investigation of Fusarium damage in wheat using hyperspectral imaging: An independent component analysis approach

With the continuously growing world population in the 21st century, the agri-food industry is in dire need of adopting rapid, eco-friendly, and reliable technologies to improve the quantity, quality, and safety of agri-food products to fulfill the world's future food needs. Hyperspectral imaging (HSI), a technique to glean a sample's spectral and spatial information, is an emerging non-destructive technique that can characterize the quality parameters of agri-food products such as Fusarium damage. Despite its vast potential, HSI systems suffer from enormous data sizes, requiring high computational time and power. One potential solution to overcome the aforementioned challenge is to reduce the data size by removing redundant information. However, detecting small optimum features from a large dataset is not trivial. To this end, an exploratory novel HSI data reduction and analysis technique was investigated and validated to identify Fusarium damage in wheat kernels. Wheat samples at three moisture contents (19, 27, and 35%, wet basis) and seven infection levels (ranging from 0 to 56 days after infection) were imaged at 256 equally spaced wavelengths from 820 to 1666 nm. Firstly, complete HSI data was utilized to successfully characterize sound and Fusarium-damaged wheat kernels using independent component analysis (ICA) algorithm. Then, a genetic algorithm optimization approach was used to reduce the data to ten wavelengths for ICA-based analysis. This data reduction approach reduced the computation time to approximately 1.31% of the original time taken for analyzing the full HSI data without compromising the performance of the system. This preliminary study suggests that such wavelength tailoring could reduce the complexity and price of the imaging hardware, e.g., the use of inexpensive non-tunable filters, and less expensive computational hardware, thereby enabling fast and affordable real-time exploration and sorting of grains. This study, while exploratory, fosters advancements in HSI data processing and identifies certain limitations that open new avenues for future research.

Design of reconfigurable multiplier-less filter structure based on IFIR for digital channelizer

The flexibility in frequency allocation is essential for high throughput satellites (HTS). The digital channelizer based transponder system has a crucial role in enhancing the performance of HTS. In this work, the design and implementation of a low computational complexity digital channelizer for HTS is proposed. The proposed reconfigurable filter structure for digital channelizer is to generate non-uniform and sharp transition width FIR filters for transponder of the satellite systems. The multipliers and group delay needed in the digital channelizer that employ the proposed structure are reduced when compared to FRM and traditional IFIR based digital channelizer. An example is used to illustrate the effectiveness of the proposed design. Results reveal that the proposed structure has a lower multiplier complexity than existing techniques. The proposed structure once implemented effectively, the power dissipation and hardware complexity are reduced. With the help of CSD, MOABC, and SIDC-CSE optimization, the filters used in this structure are made multiplier-less. Hence this structure is adaptable for the digital channelizer in the transponder of the satellite communication systems.

Kryptonite: Worst-Case Program Interference Estimation on Multi-Core Embedded Systems

Due to the low costs and energy needed, cyber-physical systems are adopting multi-core processors for their embedded computing requirements. In order to guarantee safety when the application has real-time constraints, a critical requirement is to estimate the worst-case interference from other executing programs. However, the complexity of multi-core hardware inhibits precisely determining the Worst-Case Program Interference. Existing solutions are either prone to overestimate the interference or are not scalable to different hardware sizes and designs. In this paper we present Kryptonite , an automated framework to synthesize Worst-Case Program Interference (WCPI) environments for multi-core systems. Fundamental to Kryptonite is a set of tiny hardware-specific code gadgets that are crafted to maximize interference locally. The gadgets are arranged using a greedy approach and then molded using a Reinforcement Learning algorithm to create the WCPI environment. We demonstrate Kryptonite on the automotive grade Infineon AURIX TC399 processor with a wide range of programs that includes a commercial real-time automotive application. We show that, while being easily scalable and tunable, Kryptonite creates WCPI environments increasing the runtime by up to 58% for benchmark applications and 26% for the automotive application.

Learned-SBL-GAMP based hybrid precoders/combiners in millimeter wave massive MIMO systems.

In Millimeter-Wave (mm-Wave) massive Multiple-Input Multiple-Output (MIMO) systems, hybrid precoders/combiners must be designed to improve antenna gain and reduce hardware complexity. Sparse Bayesian learning via Expectation Maximization (SBL-EM) algorithm is not practically feasible for high signal dimensions because estimating sparse signals and designing optimal hybrid precoders/combiners using SBL-EM still provide high computational complexity for higher signal dimensions. To overcome the issues of high computational complexity along with making it suitable for larger data sets, in this paper, we propose Learned-Sparse Bayesian Learning with Generalized Approximate Message Passing algorithm (L-SBL-GAMP) algorithm for designing optimal hybrid precoders/combiners suitable for mmWave Massive MIMO systems. The L-SBL-GAMP algorithm is an extension of the SBL-GAMP algorithm that incorporates a Deep Neural Network (DNN) to improve the system performance. Based on the nature of the training data, the L-SBL-GAMP can design the optimal Hybrid precoders/combiners, which enhances the spectral efficiency of mmWave massive MIMO systems. The proposed L-SBL-GAMP algorithm reduces the iterations, training overhead, and computational complexity compared to the SBL-EM algorithm. The simulation results unveil that the proposed L-SBL-GAMP provides higher achievable rates, better accuracy, and low computational complexity compared to the existing algorithm, such as Orthogonal Matching Pursuit (OMP), Simultaneous Orthogonal Matching Pursuit (SOMP), SBL-EM and SBL-GAMP for mmWave massive MIMO architectures.

Reliable Gamma-Interconnection Network for Data Analysis in Sensor Networks: Design and Performance Evaluation

In today’s era of high speed 5G internet all electronic sensor networks are connected through IoT. Bank transactions are digitized, people can access any data through their mobile phones, organizations and companies handle their projects through online meetings etc. Military and medical surveillance, navy navigation, weapon controlling, weather forecasting etc. involve big data analysis collected from sensors, that too at a very high speed with reliable results. This requires large number of parallel processors connected with huge Bank of memory modules to store big data. Reliable interconnection network is needed to connect these large number of parallel processors and memory modules efficiently hence Multistage Interconnection Networks (MINs) come into play, as they provide highly reliable communication for big data transfer between processors and memory modules whenever required. In this manuscript a new network named Reliable Gamma-interconnection Network (RGN) is introduced which possesses multiple paths between processors and memory modules with two totally disjoint path availability. It provides high reliability and minimum path distance between source node to destination node than other gamma networks known, with the minimum hardware complexity. Reliability estimation and evaluation of RGN has been presented in this paper and comparison of results achieved with other gamma networks has been done for validation purpose.

Scalable Metamaterial Integrated Digital Coding Transmitting Bit Array for Concurrent Multistream Direct Antenna Modulation

This letter presents a new type of metamaterial (MTM) integrated digital coding transmitting bit array for wireless communication. The proposed transmitter directly modulates the baseband digital signal on the carrier frequency to each antenna element without using any RF mixers as in conventional homodyne or heterodyne transmitters, thereby simplifying the hardware complexity. Single-tone carrier wave is distributed by an MTM-based power divider and fed to each antenna element of the bit array, the phase of which can be electrically manipulated to realize direct antenna modulation (DAM). Moreover, the code-division multiple access (CDMA) communication method is leveraged to achieve the concurrent multistream data transmission without increasing the hardware intricacy of the system. Experimental verification for concurrently transmitting three different data streams is carried out to demonstrate the validity of the proposed MTM integrated transmitting bit-array architecture.

Resource-Efficient Low-Latency Modified Pietra-Ricci Index Detector for Spectrum Sensing in Cognitive Radio Networks

In this article, the modified Pietra-Ricci index detector (mPRIDe) is devised, and its field programmable gate array (FPGA) and application-specific integrated circuit (ASIC) designs are reported. The mPRIDe attains lower implementation complexity with respect to its predecessor, without performance penalty. Moreover, the mPRIDe is blind, robust against time-varying noise and received signal powers, and exhibits the constant false alarm rate property. Two versions of the mPRIDe, namely mPRIDe v1 and mPRIDe v2, have been designed. The former privileges lower hardware complexity, whereas the latter aims lower latency, with both versions having a linear scalability with the number of sensors in cooperation. In comparison with the smallest area consumed by a state-of-the-art sensor, mPRIDe v1 and mPRIDe v2 consume 56.6% and 47.3% lower areas, respectively. The sensing times of the proposed sensors are 1.6 and 2.9 times better than the fastest sensing time of contemporary sensors. Moreover, the proposed designs deliver the lowest area-time-product and power-delay-product among state-of-the-art implementations. These metrics make both mPRIDe v1 and mPRIDe v2 the most hardware-efficient and power-efficient sensors reported in the literature.

Parallel adder-subtractor on elements of neural logic

Modern universal computing machines are capable of implementing any algorithm, but when solving certain tasks in terms of processing speed, they cannot compete with specialized computing modules that can increase the speed of performing arithmetic operations by using parallelism in data processing. The reliability of arithmetic calculators increases due to the use of neural-like elements. Specialized devices effectively solve array processing tasks, artificial intelligence tasks, and are used as control devices. The developed structure of a parallel adder-subtractor based on neural logic elements ensures high performance and reliability. The structural and functional schemes of the adder/subtractor blocks allow to increase the speed in comparison with the known sequential action adder when added in additional codes by at least 2 times, and with a parallel adder with sequential transfer by at least 1.5 times. It is shown that the hardware complexity of the presented adder-subtractor is 1.3 times lower compared to the sequential action adder and 2.8 times lower compared to the parallel adder with sequential transfer. The proposed structure of the adder-subtractor provides an increase in the calculation speed of arithmetic operations due to the implementation of parallelism in data processing.

Design of various operating devices for sorting binary data

The object of research is the process of designing hardware devices for sorting arrays of binary data using the methodology of space-time graphs. The main task that is solved in the work is the development and research of multi-cycle operating devices for sorting binary data in order to choose the optimal structure with predetermined technical characteristics for solving the sorting problem. As an example, the development of different types of structures of multi-cycle operating sorting devices by the method of «even-odd» permutation is shown and their system characteristics are determined. New structures of multi-cycle operating devices have been designed for a given sorting algorithm, and analytical expressions for calculating equipment costs and their performance have been given. A comparative analysis of the hardware and time complexity of the developed structures of devices for sorting binary numbers of various types with known implementations of algorithmic and pipeline operating devices was carried out. As a result, the proposed structures, when sorting large arrays of binary data (N&gt;128), have an order of magnitude less hardware complexity due to sequential execution of the same type of operations. The time complexity of multi-cycle operating devices of combined and sequential types with large values of input data is 2.3 and 3.4 times less than that of known pipeline operating devices. A feature of the research results is the possibility of finding the optimal ratio between the hardware and time characteristics of the resulting structures of sorting devices. Owing to this, the designer will be able to choose the necessary type of device for the implementation of the corresponding task with optimal system characteristics. The field of application of the designed sorting devices is the tasks of digital processing of signals and images. The practical use of the developed sorting devices can be carried out in the form of their synthesis on software integrated logic circuits

Machine Learning for Self-Coherent Detection Short-Reach Optical Communications

Driven by emerging technologies such as the Internet of Things, 4K/8K video applications, virtual reality, and the metaverse, global internet protocol traffic has experienced an explosive growth in recent years. The surge in traffic imposes higher requirements for the data rate, spectral efficiency, cost, and power consumption of optical transceivers in short-reach optical networks, including data-center interconnects, passive optical networks, and 5G front-haul networks. Recently, a number of self-coherent detection (SCD) systems have been proposed and gained considerable attention due to their spectral efficiency and low cost. Compared with coherent detection, the narrow-linewidth and high-stable local oscillator can be saved at the receiver, significantly reducing the hardware complexity and cost of optical modules. At the same time, machine learning (ML) algorithms have demonstrated a remarkable performance in various types of optical communication applications, including channel equalization, constellation optimization, and optical performance monitoring. ML can also find its place in SCD systems in these scenarios. In this paper, we provide a comprehensive review of the recent progress in SCD systems designed for high-speed optical short- to medium-reach transmission links. We discuss the diverse applications and the future perspectives of ML for these SCD systems.

Quality of Security Guarantees for and with Physical Unclonable Functions and Biometric Secrecy Systems.

Unique digital circuit outputs, considered as physical unclonable function (PUF) circuit outputs, can facilitate a secure and reliable secret key agreement. To tackle noise and high correlations between the PUF circuit outputs, transform coding methods combined with scalar quantizers are typically applied to extract the uncorrelated bit sequences reliably. In this paper, we create realistic models for these transformed outputs by fitting truncated distributions to them. We also show that the state-of-the-art models are inadequate to guarantee a target reliability level for all PUF outputs, which also means that secrecy cannot be guaranteed. Therefore, we introduce a quality of security parameter to control the percentage of the PUF circuit outputs for which a target security level can be guaranteed. By applying the finite-length information theory results to a public ring oscillator output dataset, we illustrate that security guarantees can be provided for each bit extracted from any PUF device by eliminating only a small subset of PUF circuit outputs. Furthermore, we conversely show that it is not possible to provide reliability or security guarantees without eliminating any PUF circuit output. Our holistic methods and analyses can be applied to any PUF type, as well as any biometric secrecy system, with continuous-valued outputs to extract secret keys with low hardware complexity.