Parallel adder-subtractor on elements of neural logic

Abstract

Modern universal computing machines are capable of implementing any algorithm, but when solving certain tasks in terms of processing speed, they cannot compete with specialized computing modules that can increase the speed of performing arithmetic operations by using parallelism in data processing. The reliability of arithmetic calculators increases due to the use of neural-like elements. Specialized devices effectively solve array processing tasks, artificial intelligence tasks, and are used as control devices. The developed structure of a parallel adder-subtractor based on neural logic elements ensures high performance and reliability. The structural and functional schemes of the adder/subtractor blocks allow to increase the speed in comparison with the known sequential action adder when added in additional codes by at least 2 times, and with a parallel adder with sequential transfer by at least 1.5 times. It is shown that the hardware complexity of the presented adder-subtractor is 1.3 times lower compared to the sequential action adder and 2.8 times lower compared to the parallel adder with sequential transfer. The proposed structure of the adder-subtractor provides an increase in the calculation speed of arithmetic operations due to the implementation of parallelism in data processing.