Abstract

The object of research is the process of designing hardware devices for sorting arrays of binary data using the methodology of space-time graphs. The main task that is solved in the work is the development and research of multi-cycle operating devices for sorting binary data in order to choose the optimal structure with predetermined technical characteristics for solving the sorting problem. As an example, the development of different types of structures of multi-cycle operating sorting devices by the method of «even-odd» permutation is shown and their system characteristics are determined. New structures of multi-cycle operating devices have been designed for a given sorting algorithm, and analytical expressions for calculating equipment costs and their performance have been given. A comparative analysis of the hardware and time complexity of the developed structures of devices for sorting binary numbers of various types with known implementations of algorithmic and pipeline operating devices was carried out. As a result, the proposed structures, when sorting large arrays of binary data (N>128), have an order of magnitude less hardware complexity due to sequential execution of the same type of operations. The time complexity of multi-cycle operating devices of combined and sequential types with large values of input data is 2.3 and 3.4 times less than that of known pipeline operating devices. A feature of the research results is the possibility of finding the optimal ratio between the hardware and time characteristics of the resulting structures of sorting devices. Owing to this, the designer will be able to choose the necessary type of device for the implementation of the corresponding task with optimal system characteristics. The field of application of the designed sorting devices is the tasks of digital processing of signals and images. The practical use of the developed sorting devices can be carried out in the form of their synthesis on software integrated logic circuits

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