Abstract
The optimal binary number sorting algorithms for hardware realization are analyzed. Spatial-temporal synthesis of the parallel structure of the sorting algorithm of 16th binary numbers by the method of perfect interleaving with the use of spatial and temporal graphs has been carried out. Stream, conveyor and recursive structures of binary number sorting devices are constructed. The analytical expressions for determining of the hardware and time complexity of these devices were obtained and their comparative analysis was carried out. As a result of the theoretical studies, it has been shown that the recursive sorting device has 10,8 times less hardware complexity than the conveyor structure. In the practical implementation of these devices in the VHDL language of and their synthesis on the FPGA, the results of experimental studies are close to theoretical calculations.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
