Hard Real-time Systems Research Articles

A Fault-Tolerant Ethernet for Hard Real-Time Adaptive Systems

Distributed embedded systems (DESs) that perform critical tasks in unpredictable environments must be reliable, hard real-time, and adaptive. Since a DES comprises nodes that rely on a network, the network must provide adequate support: it must be reliable, convey messages on time, and meet new real-time requirements as the nodes adapt. Ethernet is ill-suited for such hard real-time adaptive systems, but it can be made suitable. The flexible time-triggered (FTT) paradigm already supports hard real-time message exchanges and the necessary flexibility to meet evolving hard real-time requirements, but its Ethernet implementations had reliability limitations. To address these, we designed FTT replicated star for Ethernet (FTTRS), a communication subsystem that tolerates permanent and transient faults, even if they occur simultaneously, while keeping the paradigm's key features: support for both the timely exchange of periodic and sporadic real-time messages, and support for updating the real-time parameters of these messages at runtime. In this paper, we present FTTRS, the first Ethernet-based communication subsystem specifically designed for highly reliable hard real-time adaptive DESs.

Side-channel protected MPSoC through secure real-time networks-on-chip

The integration of Multi-Processors System-on-Chip (MPSoCs) into the Internet-of-Things (IoT) context brings new opportunities, but also represent risks. Tight real-time constraints and security requirements should be considered simultaneously when designing MPSoCs. Network-on-Chip (NoCs) are specially critical when meeting these two conflicting characteristics. For instance the NoC design has a huge influence in the security of the system. A vital threat to system security are so-called side-channel attacks based on the NoC communication observations. To this end, we propose a NoC security mechanism suitable for hard real-time systems, in which schedulability is a vital design requirement. We present three contributions. First, we show the impact of the NoC routing in the security of the system. Second, we propose a packet route randomisation mechanism to increase NoC resilience against side-channel attacks. Third, using an evolutionary optimisation approach, we effectively apply route randomisation while controlling its impact on hard real-time performance guarantees. Extensive experimental evidence based on analytical and simulation models supports our findings.

A Computational Model to Implement Binaural Synthesis in a Hard Real-Time Auditory Virtual Environment

There is a growing interest in the development and the evaluation of real-time auditory virtual environments (AVE). The implementation of this type of simulation system in general purpose computers is a still a challenge, and there are few studies that evaluated the perceived quality of synthetized sounds of simulated acoustic scenes. To evoke in the listener a correct image of the modeling space, the system must be dynamic and interactive. That is, it must respond to the changes in the acoustic scenario produced by the listener movement, in a perceptually acceptable time and with an update rate that guarantees continuity in the reproduction of sound events. Hard real-time systems ensure that a given task runs within a given time interval, providing deterministic behavior for applications with time restrictions. In the current article, a computational model to implement binaural synthesis in a hard real-time AVE is presented and evaluated. The computer model was implemented in an open-source auralization system. Measurements and real-time simulations on a university classroom were carried out to perform a reverberation time parameters validation and a system performance evaluation. Also, measured and simulated binaural soundtracks (composed from anechoic stimuli) were compared in terms of three selected perceptual attributes for subjective evaluations of static positions. The results showed that real-time performance was acceptable according to values previously reported in the literature and that computer prediction errors for the measured parameters were within the subjective difference limens. The computational model was able to generate an AVE with an acceptable overall perceptual quality.

Debugging and monitoring of applicationprograms in the BagrOS-4000 real-time operation system based on the Elbrus architecture

The article is concerned with the problems of monitoring and debugging of operating system processes, the effectiveness of which in the hard real-time operating system version does not allow any stopping to analyze the state of software and/ or hardware. The paper describes the concept of a debugging and monitoring system developed taking into account this feature in the Sukhoi design bureau for the BagrOS-4000 hard real-time operating system on the Elbrus architectural platform together with the specialists of MCST JSC. The method of non-stop monitoring and data collection in hard realtime processes in the multiprocess multimodular systems is discussed. An approach to the management of debugging targets in terms of source code using the DWARF debugging information specification is presented. The transition from the instrumental machine to the system server built into the target computer is described. Given the rationale for the use of client-server architecture in the debugging and monitoring system for BagrOS-4000. A comparative analysis of the key functionality of the debugging and monitoring system with the existing debugging systems has been carried out; the key aspects of the DMS architecture have been considered. The design of a machine-dependent interface required for the integration of the independent hardware platforms into the BagrOS-4000 system when implementing the system on an integrated avionics module of the onboard complex is discussed. The results of testing of the debugging and monitoring systems are analyzed in terms of efficiency versus the classical method of using the debug console prints when debugging a real-time operating system. Most of the above solutions are universal and have been successfully tested using other microprocessor platforms on multi-threaded application programs of real-time operating systems running on multi-core processors, including the MIPS, Power PC, Intel platforms.

Hardlock: Real-time multicore locking

Multiple threads executing on a multicore processor often communicate via shared objects, allocated in main memory, and protected by locks. A lock itself is often implemented with the compare-and-swap operation. However, this operation is retried when the operation fails and the number of retries is unbounded. For hard real-time systems we need to be able to provide worst-case execution time bounds for all operations. The paper presents a time-predictable solution for locking on a multicore processor. Hardlock is an on-chip locking unit that supports concurrent locking without the need to get off-chip. Acquisition of a lock takes 2 clock cycles and release of a lock 1 clock cycle.

DPVFS: a dynamic procrastination cum DVFS scheduler for multi-core hard real-time systems

Optimising energy consumption has become the primary focus of research in recent years. Static and dynamic energy optimisation during task scheduling is one of the most prominent measures available. This is achieved mainly by shutdown and slowdown techniques. In uni-processor real-time systems, the most widely used shutdown and slowdown techniques are dynamic procrastination (DP) and dynamic voltage and frequency scaling (DVFS). This paper proposes DPVFS a hard real-time task scheduler for multi-core (MC) system to optimise overall energy consumption without deadline misses. DPVFS combines DP and DVFS for MC systems to save overall energy consumption. DPVFS shuts the processor down whenever possible with the help of procrastination. If shutdown is not possible, it adjusts the voltage and frequency to reduce dynamic energy consumption. The experimental evaluation of DPVFS with synthetically generated benchmark program suites shows savings of 18.8% and 33.2% of overall energy over DP based schedulers and DVFS based schedulers respectively.

Safe and efficient power management of hard real-time networks-on-chip

The power overhead of Networks-on-Chip (NoCs) becomes tremendous in high density Multiprocessor Systems-on-Chip (MPSoCs). Especially in hard real-time and safety-critical systems, power management mechanisms must be developed and efficiently adhered to real-time requirements. However, state-of-the-art solution typically induces a high timing overhead, thus challenging safety, or has limited power saving capabilities. Additionally, current power-gating mechanisms do not provide an upper bound of the latency overhead, and thus no timing guarantees. We propose a safe and enhanced approach for power-gating that allows a global and dynamic power management under timing guarantees, i.e., all deadlines of critical tasks are met. It introduces a control-layer to save power on the NoC data layer using multiple Power-Aware Traffic-Monitor (PATM) units, which apply knowledge of the global state of the system to efficiently save power on NoC routers even at high NoCs utilizations. To safely apply the PATMs in hard real-time systems while meeting the deadlines, we provide a formal worst-case timing analysis to derive PATMs upper bound latency overhead. Experimental results show that our approach efficiently reduces static power consumption, and provides scalability inducing very small area overhead.

Energy-Efficient Multicore Scheduling for Hard Real-Time Systems

As real-time embedded systems are evolving in scale and complexity, the demand for a higher performance at a minimum energy consumption has become a necessity. Consequently, many embedded systems are now adopting multicore architectures into their design. However, scheduling on multicores is not a trivial task and scheduling to minimize the energy consumption further increases the complexity of the problem. This problem is especially aggravated for hard real-time systems where failure to meet a deadline can be catastrophic. Such scheduling algorithms yearn for a polynomial time complexity for the task-to-core assignment problem with an objective to minimize the overall energy consumption. There is now a trend toward heterogeneous multicores where cores differ in power, performance, and architectural capabilities. The desired performance and energy consumption is attained by assigning a task to the core that is best suited for it. In this article, we present a survey on energy-efficient multicore scheduling algorithms for hard real-time systems. We summarize various algorithms reported in the literature and classify them based on Partitioned, Semi-Partitioned, and Global scheduling techniques for both homogeneous and heterogeneous multicores. We also present a detailed discussion on various open issues within this domain.

Memory management of safety-critical hard real-time systems designed in SystemJ

SystemJ is a programming language based on the Globally Asynchronous Locally Synchronous (GALS) Model of Computation (MoC) used to design safety critical hard real-time systems. SystemJ uses the Java programming language as the “host” language, for carrying out data computations, because Java provides clearly defined operational semantics, type and memory safety in the form of the Garbage Collector(GC), which help with formal functional verification. The same GC, which helps in functional verification, makes Worst Case Reaction Time (WCRT)11Similar to Worst Case Execution Time. analysis challenging. Any WCRT analysis framework for GALS programs needs to consider the operations performed by the host language. It has been shown that the worst case time estimates for garbage collection cycles are in seconds, whereas the program’s WCRT itself is in micro-seconds. These pessimistic estimates render the WCRT analysis framework ineffective. In order to overcome this problem, we develop a compiler assisted memory management technique for applications written in SystemJ. The SystemJ MoC plays the central role in the proposed technique. The SystemJ MoC allows clearly demarcating the state boundaries of the program, which in turn allows us to partition the heap, at compile time, into two distinct areas: (1) the memory area called the permanent heap, which holds objects that are alive throughout the life time of the application, and (2) the memory area used to hold all other objects, called the transient heap. The size of these memory areas are bounded statically. Furthermore, the memory allocation and reclaim procedures are simple load and pointer reset operations, respectively, which are guaranteed to complete within a bounded number of clock-cycles, thereby alleviating the need for large pessimistic WCRT bounds obtained due to the GC. Experimental results also show that the proposed approach is approximately three times faster, in terms of memory allocation times as compared to standard real-time GC approaches.

A Unified Framework for Period and Priority Optimization in Distributed Hard Real-Time Systems

Modern embedded systems, such as automotive, are physically distributed with an increasing number of microcontrollers and buses. They support complex functions such as active safety and autonomous driving features with a high degree of data dependencies. The most common configuration uses periodic activation of tasks and messages coupled with priority-based scheduling. Selecting task and message parameters so that end-to-end deadlines are met can be very challenging, since such deadlines are enforced across a set of microcontrollers and buses. In this paper, we address the problem of optimal selection of task and message activation periods and priorities. Existing approaches cannot scale to large designs and have to settle to optimize period or priority separately, largely due to the complexity of response time analysis techniques. Instead, we present a new, unified framework that simultaneously optimizes period and priority assignment. It avoids the pitfalls of existing approaches by abstracting the response time calculation with the new concept of maximal unschedulable period and deadline assignment. We demonstrate with two industrial case studies that our approach runs magnitudes faster than existing approach on period optimization, while providing substantially better solutions.

Analysis techniques for supporting hard real-time sporadic gang task systems

This paper first studies the problem of scheduling hard real-time sporadic gang task systems under global earliest-deadline-first on a multiprocessor platform, where a gang application’s threads need to be concurrently scheduled on distinct processors. A novel approach combining new lag-based reasoning and executing/non-executing gang interval analysis technique is introduced, which is able to characterize the parallelism-induced idleness, as a key challenge of analyzing gang task schedules. To the best of our knowledge, this approach yields the first utilization-based test for hard real-time gang task systems. To further handle the clustered scheduling scenario, we propose a partitioning scheme that enables a set of gang tasks to be efficiently assigned and scheduled among multiple clusters.

EUROPEAN TEMPUS TATU PROJECT AND WIRESHARK SOFTWARE IN INDUSTRIAL NETWORKS DATA TRANSFER PROTOCOLS STUDYING AND ANALYZING

Industrial data transfer technologies are implementing in industry, transport, energetic together with Industry 4.0 and IIoT concepts. Compatible with previous generations TCP/IP based protocols ProfiNet, ModBus/TCP, Ethernet/IP, EtherCAT were created to perform complex technical systems remote control. 
 In 2013 – 2017 European TEMPUS TATU (Trainings in Automation Technologies for Ukraine) project was realized and TATU Smart Lab (TSL) equipment was obtained. 
 TSL is a set of devices for modern automation technologies studying. It matches to Industry 4.0 and IIoT concepts. It contains programmable logic controllers, I/O devices, switches, wireless access points and can be used for studying of Ethernet based data transfer technologies, wireless data transfer, TCP/IP technologies, hard real-time systems, EtherCAT, CAN, RS232/485, PROFINET, Modbus TCP interfaces.
 Wireshark software allows to analyze network traffic and supports capturing of long network protocols list. It helps to understand the reason of network problems, simplifies industrial and corporate networks exploitation.

PSO based optimization of worst-case execution time for ASIP application

Industrial requires hard real-time systems for safety and critical applications like automotive, Aeronautics, manufacturing control and train industries. Hard Real-Time Systems’ embedded controllers are with expectation of complete the tasks within a certain time bounds reliably including task scheduling. The estimation of upper bound limits corresponding to the execution times is often termed as the Worst-Case Execution Times (WCETs). It is an essential step in developing and validating the hard real-time systems. Particularly, the upper bounds need to satisfy these constraints related to the execution times. However, it is often not feasible many times to set upper bounds on execution times for programs. In present work, the problem of choosing reconfigurable Custom Instructions (CIs) is accomplished by optimizing the WCET corresponding to an application. This issue is designed using Particle Swarm Optimization (PSO) based program for a path analysis. The work emphasizes on the effectiveness of optimizing the WCET when applied to a reconfigurable processor. It evaluates a compound application of multimedia with a host of reconfigurable CIs corresponding to a number of hardware parameters.

Storage capacity for EDF–ASAP algorithm in energy-harvesting systems with periodic implicit deadline hard real-time tasks

Abstract In this paper, a hard real-time system with a single processor that is supplied by a renewable energy source and has a limited capacity storage unit is addressed. Tasks are supposed to be periodic implicit deadline in which execution of tasks must be completed before their deadline and deadline of tasks are at the end of their period. Storage units suffer from leakage moreover power rate of harvesting energy is not precisely predictable. Therefore, scheduling algorithms that are able to schedule tasks as well as consume stored energy as soon as possible are superior in performance. Online EDF–ASAP algorithm that is an energy-constraint-aware derivative of Earliest Deadline First (EDF) is considered in this paper. First, a method to calculate storage unit size for EDF–ASAP algorithm, scheduling energy-harvesting systems is proposed. Another fine storage size adjusting method for low processor utilization task sets is also proposed. Then ability of EDF–ASAP to schedule implicit deadline hard real-time tasks up to processor utilization of 100% and energy utilization of 100% using this fully charged storage unit is proved. Finally, an extensive simulation validates the efficiency of proposed calculation method and compares minimum sufficient storage size with calculated one.

An improved formalization analysis approach to determine schedulability of global multiprocessor scheduling based on symbolic safety analysis and statistical model checking in smartphone systems

Modern smart phones are typically equipped with multicore processors. In this paper, we address the problem of determining schedulability of a real-time periodic taskset with fixed release offsets and possible release jitters on a multicore processor with global Fixed-Priority (FP) or EDF (Earliest Deadline First) scheduling algorithms, using the model-checker UPPAAL for Timed Automata. In addition to yes/no schedulability analysis for hard real-time systems, we also apply statistical model checking to estimate the probability of unschedulability for soft real-time systems, described with two statistical parameters (confidence and accuracy).

Модель целеполагания в многоагентной системе с ограниченным ресурсом времени

The article considers the goal-setting model concept in modeling the reasoning of cognitive agents in dynamic hard real-time systems. An important issue concerned with processing tasks by means of hard real-time systems is the ability to estimate the amount of time available for processing till the moment of time it becomes too late to produce the result. To avoid such a situation, it is necessary to be able to correlate the steps and results of ongoing reasoning with the events occurring in the external environment. Reasoning of this type is called reasoning in time. To formalize such reasoning, formalisms of active logic are suggested. When regarded as a deduction model, active logic is characterized by a language and a set of deductive rules and observations. By using an observation function, one can model a dynamic environment, information about which arrives to the agent as changes occur in that environment. Reasoning in time is characterized by accomplishment of deduction cycles (steps) serving as a time standard. The agent's knowledge is associated with the index of the step on which it was gained for the first time. Observations can be carried out at any step of the deductive process, and a formula expressing some statement and associated with the relevant step serves as its result. To construct a goal-setting model for solving problems in hard real-time environment, a logic system (a metalogic of knowledge) is introduced to formalize in the general case the metareasoning of several intellectual agents about the tasks they face, about their own knowledge, and about the possibilities of solving these problems in interaction with the other agents, taking into account the limited time resource available to each of the agents. The goal-setting process gives an answer to the question of which subgoals and in what sequence at a given moment in time should be achieved for the main goal faced by the multi-agent system be fulfilled within acceptable time. It should be noted that the response may vary depending on the current situation and as additional information becomes available, because the assigned targets may be canceled and new ones assigned. The knowledge metalogics language is shown as a combination of three languages: the language of problem domain, the language of agents, and metalanguage, with the last two being multigrade ones. The language of agents contains special predicate symbols for reasoning about goals, about the tasks associated with them, about the structure of these tasks, and about possible methods and admissible timeframes for solving them. Metalanguage allows one to express general statements about the arguments of agents. Formal theories constituting the meta-knowledge system of knowledge are presented.

Communication Technologies and Network Protocols of Automotive Systems

Automotive industry has gone through rapid changes in the past few years. The usage of electronics and electronic control units (ECUs) have increased manifold, and this has also affected the way different subsystems communicate. Communication technologies and protocols are required to fulfill demands of fault-tolerance, dependability, bandwidth and determinism of demanding and safety-critical applications. This paper presents a survey of state-of-the-art and the most commonly employed communication technologies and protocols; both wired and wireless for in-vehicle and vehicle to vehicle (V2V) communication in the automotive systems. The technologies such as LIN (Local Interconnect Network), CAN (Controller Area Network), MOST (Media Oriented Systems Transport), and Flexray are compared in terms of the performance, reliability, cost and protocol characteristics. The study shows that Flexray is an excellent network topology for in-vehicle communication that has higher degree of fault tolerance, and is suitable for hard real time systems with high bandwidth. Moreover, wireless technologies i.e. Bluetooth, ZigBee, Wi-Fi and UWB are discussed that satisfy different requirements of diagnostics and multimedia communication for in-vehicle and vehicle to vehicle communication and can be used for advanced autonomous driving systems. The paper also presented issues that need to be addressed to fully realize the potential of these communication technologies and other advancements in automotive industry.

On the analysis of random replacement caches using static probabilistic timing methods for multi-path programs

Probabilistic hard real-time systems, based on hardware architectures that use a random replacement cache, provide a potential means of reducing the hardware over-provision required to accommodate pathological scenarios and the associated extremely rare, but excessively long, worst-case execution times that can occur in deterministic systems. Timing analysis for probabilistic hard real-time systems requires the provision of probabilistic worst-case execution time (pWCET) estimates. The pWCET distribution can be described as an exceedance function which gives an upper bound on the probability that the execution time of a task will exceed any given execution time budget on any particular run. This paper introduces a more effective static probabilistic timing analysis (SPTA) for multi-path programs. The analysis estimates the temporal contribution of an evict-on-miss, random replacement cache to the pWCET distribution of multi-path programs. The analysis uses a conservative join function that provides a proper over-approximation of the possible cache contents and the pWCET distribution on path convergence, irrespective of the actual path followed during execution. Simple program transformations are introduced that reduce the impact of path indeterminism while ensuring sound pWCET estimates. Evaluation shows that the proposed method is efficient at capturing locality in the cache, and substantially outperforms the only prior approach to SPTA for multi-path programs based on path merging. The evaluation results show incomparability with analysis for an equivalent deterministic system using an LRU cache. For some benchmarks the performance of LRU is better, while for others, the new analysis techniques show that random replacement has provably better performance.

Mission Management Computer Software for RLV-TD

The Mission Management Computer (MMC) software is responsible for the autonomous navigation, sequencing, guidance and control of the Re-usable Launch Vehicle (RLV), through lift-off, ascent, coasting, re-entry, controlled descent and splashdown. A hard real-time system has been designed for handling the mission requirements in an integrated manner and for meeting the stringent timing constraints. Redundancy management and fault-tolerance techniques are also built into the system, in order to achieve a successful mission even in presence of component failures. This paper describes the functions and features of the components of the MMC software which has accomplished the successful RLV-Technology Demonstrator mission.

Phasing of Periodic Tasks Distributed over Real-time Fieldbus

In designing a distributed hard real-time system, it is important to reduce the end-to-end delay of each real-time message in order to ensure quick responses to external inputs and a high degree of synchronization among cooperating actuators. In order to provide a real-time guarantee for each message, the related literature has focused on the analysis of end-to-end delays based on worst-case task phasing. However, such analyses are too pessimistic because they do not assume a global clock. With the assumption that task phases can be managed by using a global clock provided by emerging real-time fieldbuses, such as EtherCAT, we can try to calculate the optimal task phasing that yields the minimal worst-case end-to-end delay. In this study, we propose a heuristic to manage the phase offsets in the distributed tasks to reduce the theoretical end-to-end delay bound. The proposed heuristic reduces the search time for a solution by identifying time intervals where actual communication occurs among inter-dependent tasks. Furthermore, to analyze the distribution of endto- end delays in different phases, we implemented a simulation tool. The simulation results showed that the proposed heuristic can reduce worst-case end-to-end delay as well as jitter in end-to-end delays.