Hard Real-time Systems Research Articles

Providing spatial isolation for Mixed-Criticality Systems

Hard real-time systems, characterized by stringent timeliness requirements, occur in an increasing variety of industrial sectors. Some such domains carry important safety-critical concerns, notably avionics, space, and automotive. One common design trend across those domains seeks to reduce the number of computing devices embedded in them by integrating software applications of different criticality levels into one and the same onboard computer. A safety-savvy design approach however requires isolation among components of different criticality, to prevent unintended reciprocal interference across them. Isolation is traditionally achieved through partitioning. Partitioning, however, incurs low resource utilization as cautionary margins are used to inflate partition budgets over their anticipated needs. This situation has prompted research into alternative ways to integration that can safely afford higher levels of utilization. The Mixed-Criticality (MC) approach, which concentrates on the CPU scheduling problem, has yielded a large body of research results that show considerable gains in sustained utilization, but it has yet to meet all of the isolation requirements of safety-critical systems. This work presents a solution to augment a state-of-the-art MC solution with efficient and effective spatial isolation capabilities. Experimental results show that our solution provides adequate guarantees of temporal and spatial isolation with very small runtime overhead.

Schedulability Analysis in Fixed-Priority Real-Time Multicore Systems with Contention

In the scheduling of hard real-time systems on multicore platforms, significant unpredictability arises from interference caused by shared hardware resources. The objective of this paper is to offer a schedulability analysis for such systems by assuming a general model that introduces interference as a time parameter for each task. The analysis assumes constrained deadlines and is provided for fixed priorities. It is based on worst-case response time analysis, which exists in the literature for monocore systems. We demonstrate that the worst-case response time is an upper bound, and we evaluate our proposal with synthetic loads and execution on a real platform.

TASK SCHEDULING OPTIMISATION OF DISTRIBUTED REAL-TIME COMPUTING SYSTEMS.

Distributed computing structures for production and special purposes represent the resources of soft or hard real-time systems. The problem of task planning is to determine the optimal distribution according to the generalized criterion of system utility. The article discusses the methods of building a schedule, based on the theory of planning. It is shown that the most effective step in this process is the optimisation of the activity of the enterprises or organizations at all levels - economic, technical, informational, etc., under the conditions of natural limitations on time resources. Since the optimisation of schedule planning occupies a fundamentally important place in the process of organizing the effective operation of a distributed multiprocessor computing system, the possibilities of using this theory in creating an optimal schedule based on the theory of queues with ordinary and marked applications are considered. The theoretical basis of the planning optimisation problem is a multistage system with M storage units and a set of N´M services. In order to organize the schedule optimality criteria to ensure ease of description, storage and software implementation, a conditional division of criteria into geographic, technical or transit categories with a description of the corresponding priority value is proposed. Taking into account these components, an expression for the average waiting time in the queue for a marked demand is derived. The scheme of the conceptual approach to the construction of a multi-core computer with the distribution of periodic and sporadic tasks is presented. The scheme of the real-time system (RTS) in hardware and software implementation is also presented. Background streams in RTS are activated by RT operating system (RT OS) commands and are embedded in primary streams. The above demonstrates the versatility of the proposed approach to scheduling a multiprocessor computing structure and its ability to meet the user's work requirements in real time.

Probabilistic Safe WCET Estimation for Weakly Hard Real-time Systems at Design Stages

Weakly hard real-time systems can, to some degree, tolerate deadline misses, but their schedulability still needs to be analyzed to ensure their quality of service. Such analysis usually occurs at early design stages to provide implementation guidelines to engineers so they can make better design decisions. Estimating worst-case execution times (WCET) is a key input to schedulability analysis. However, early on during system design, estimating WCET values is challenging, and engineers usually determine them as plausible ranges based on their domain knowledge. Our approach aims at finding restricted, safe WCET sub-ranges given a set of ranges initially estimated by experts in the context of weakly hard real-time systems. To this end, we leverage (1) multi-objective search aiming at maximizing the violation of weakly hard constraints to find worst-case scheduling scenarios and (2) polynomial logistic regression to infer safe WCET ranges with a probabilistic interpretation. We evaluated our approach by applying it to an industrial system in the satellite domain and several realistic synthetic systems. The results indicate that our approach significantly outperforms a baseline relying on random search without learning and estimates safe WCET ranges with a high degree of confidence in practical time (< 23 h).

Computed tomography system with strict real-time synchronization for in-situ 3D analysis of periodically vibrating objects

In the contribution, we present a laboratory system capable of X-ray computed tomography (XCT) scanning of an periodically moving or oscillating object. The system is an in-house developed XCT setup with electromagnetic voice coil actuator mounted on top of the rotary stage of the setup. The strict synchronization of the components, the rotary stage, the electromagnetic actuator movement and the detector readout is accomplished with use of the detector hardware trigger and hard real-time Linux operating system. Cylindrical sample manufactured from epoxy resin with metal particles to enable movement tracking is scanned in a stationary position and during periodical movement induced by the vibration stage. The volumetric data of the scans is compared and the results of this contribution represent an important step towards identification of defects through modal analysis of in-situ harmonically vibrating object.

A real-time vital control module to increase capabilities of railway control systems in highly automated train operations

Recent advances in technology and railway have led to the introduction of systems and infrastructures capable of driving trains automatically. The Automatic Train Operation (ATO) system has been optimized for active human supervision. The next challenge is to realize ATO systems capable of achieving unsupervised operations on the mainlines. However, at this aim, additional safety functionalities should be provided. In this paper, we propose a pioneer hardware/software Vital Control Module (VCM) architecture capable of expanding the control capabilities of the existing train control system. The VCM includes a Printed Circuit Board (PCB), to be integrated into the cabin equipment, managed by a reliable and safe hard Real-Time Operating System (RTOS). Both hardware and software are developed to be compliant with related safety standards. The VCM integrates an application logic that acts as an on-board equipment control core, assessing the overall operativity in real-time, and promptly issuing emergency brakes if hazardous situations occur. The application logic has been developed with a model-based approach via Simulink/Stateflow tool and implemented as a C-script on the Xilinx Ultrascale + core housed on the PCB. We have used two testbeds to evaluate the VCM performance. Experimental results showed that the Worst-Case Response Time (WCRT) by the application logic is 13.6 times smaller than the most limiting specification-related deadline. The achieved earliness (− 1.8 ms out of 2 ms of deadline) allows for the easy expansion of VCM’s train protection capabilities in the future. Results from the second testbed showed that the VCM can intervene to mitigate hazardous situations ~ 2 times faster than the current automatic train protection systems according to the related standard.

Impact in the Parallel Processing of IHM-Plasma Using the Earliest-Deadline-First Algorithm for the Task-Scheduler Realized by Hardware

Abstract—This work studies the impact in the parallel processing of the Interlocked-Hardware-Microkernel (IHM) Plasma microprocessor (IHM-Plasma) by implementing the Earliest-Deadline-First (EDF) algorithm by hardware in the task-scheduler block that belongs to those task-based operational systems, such as that related to the real-time operational systems (RTOS). IHM-Plasma presents Reduced Instruction Set Computer (RISC) architecture. The main results have observed by this study show that the IHM-Plasma running the EDF algorithm by hardware has increased the tasks executed per second in 174% while running a task-based operational system with 14 active tasks in comparison to the original Plasma running the EDF algorithm by software. The developed work has great potential use in Hard Real-Time Systems and others where a rigid control of deadlines is essential and hold many tasks.

Co-Optimizing CPU Voltage, Memory Placement, and Task Offloading for Energy-Efficient Mobile Systems

Energy-saving is one of the most important missions in the design of battery-based mobile systems. Many ideas have been suggested for saving energy in different system layers. Specifically, (1) lowering the supply voltage for idle CPU time slots, (2) using hybrid memory to save DRAM refresh power, and (3) task offloading to edge/cloud servers are well-acknowledged techniques used in CPU, memory, and network subsystems. In this paper, we show that co-optimizing these three techniques is necessary for further reducing the energy consumption of mobile real-time systems. To this end, we present an extended task model and formulate the effect of dynamic voltage/frequency scaling (DVFS), hybrid memory allocation, and task offloading problems as a unified measure. We then present a new real-time task scheduling scheme, called Co-TOMS, to co-optimize the energy-saving techniques in CPU, memory, and network subsystems by considering the given task set and resource conditions. The main contributions of our study can be summarized as follows. First, we optimize three energy-saving techniques across different system layers and find that they have significant influence on each other. For example, the effect of DVFS alone is limited in mobile systems, but combining it with offloading greatly amplifies its efficiency. Second, previous studies on offloading usually define a deadline as the maximum allowable latency at the application-level, but we focus on hard real-time systems that must meet task-level deadlines. Third, we design a steady-state genetic algorithm that allows fast convergence with reasonable computation overhead under various resource and workload conditions.

Development of a method of analysis of energy and information characteristics of wireless networks of critical application under conditions of limitations on the signal/(interference plus noise) ratio

The object of the research, the results of which are presented in the article, is the process of analyzing the energy and information characteristics of wireless networks of critical application. The presented article examines the problems of information and telecommunication systems of air transport as hard real-time systems. Thanks to the development of methods for analyzing the bandwidth of heterogeneous networks that function under the conditions of external interference, caused, among other things, by the random nature of multiple access, the asymptotic characteristics of networks and their dependence on the number of network and terminal nodes, the size of the network as a whole, were obtained. The specificity of wireless networks is the propagation of signals through a free environment, that is, fundamentally open access to signals as carriers of information that is transmitted from one subscriber to another. Based on the results of the analysis of promising information and communication and computer networks of critical application, it was found that the main problems for networks are their vulnerability to external interference of various origins, which worsens QoS indicators, in particular, performance. Therefore, in addition to the general problems of managing information and telecommunication networks, the problems of protection against unauthorized interference and external interference of various origins are quite acute in wireless networks. In order to constantly monitor network characteristics at the proper level, a method of calculating the current signal/(interference plus noise) ratio has been developed. According to the results of the analysis of the energy and information characteristics of the network, their relationship is established, which is not always obvious, but very indicative and useful, for example, for solving the tasks of multi-criteria optimization of parameters and management of the network state.

Real-Time Synchronization System for Press Machines

A real-time system is one that is put through its paces, meaning that it responds within the allotted time frame or fulfills the deadline. There are two sorts of real-time systems: hard and soft. Both are employed in various situations. When using hard real-time systems, even a delay of a few nanoseconds or microseconds is not permitted. Soft real-time systems offer some leeway in the depiction of time. Modern industries rely heavily and extensively on real-time systems. In order to produce the most precise and accurate results, systems are built to operate in real time. Real-time systems have a significant influence on human health and treatment in the realm of medical science. Real-time systems in medical science have saved countless lives and allowed for the more straightforward treatment of complicated diseases. This research proposal is centred on a "Real-time synchronization system for press machines" to regulate the machines for manufacturing if the number of workpieces exceeds and enable or disable the machines, utilizing sensors, controllers, and more parts. This real-time synchronization system is dependable and reasonably priced; it can be applied to industrial settings or other settings. This system has good sustainability; two press tool machines can use the system.

A systematic review on security aware real-time task scheduling

Nowadays, security and scheduling are the most crucial aspects of each distributed real-time application due to the rapidly enhanced use of such applications. This study presents a systematic literature review (SLR) on security and scheduling techniques for real-time applications in homogeneous and heterogeneous environments and to identify areas that need more attention for a wide range of applicability of real-time applications. The search procedure identified 3162 articles, and 103 best relevant articles are selected based on quality assessment scores for a brief review and discussions with the area experts or academicians. This study considers articles with a quality assessment score of more than five for a brief review. Hence, the applications related to security, scheduling, load balancing, fixed priority, task, job, and packet scheduling, and deadline constraints of soft and hard real-time systems in homogeneous and heterogeneous environments as per the state-of-the-art have been discussed. This discussion provides a better understanding of the real-time applications. The survey thus, aims to present the improvements in real-time task scheduling with security constraints in different distributed computing environments. The SLR also highlights various real-time task scheduling algorithms/techniques including the role of security. This SLR also provides meaningful and valuable study to the researchers by providing brief studies of various real-time task scheduling algorithms and security needs in tabular form.

Development of a Low-Cost Relay Prototype for Real-Time Power Protection Functions

This paper presents a Raspberry Pi 3B+ based low-cost universal relay able to run power protection functions in real-time. The configurations necessary for this single-board computer to be able to provide real-time response are shown, as for latency tests to verify its response time. An experimental circuit was built to send three-phase fault signals from a Relay tester to the low-cost relay, in order to evaluate its response time to clear faults in comparison to a commercial relay. A neural networks algorithm was developed and executed in real-time by the proposed low-cost relay, which is able to differentiate three-phase faults from transient signals created from large load variations. The results show that the low-cost relay is capable of running simple and complex protection functions within a pre-defined runtime and acceptable precision, compared to a commercial protection relay. However, the sampling frequency the low-cost relay is able to handle is limited. The results have also shown that the low-cost relay meet the requirements for a soft real-time system, which is not ideal for practical power protection systems that require hard real-time systems.

Evolving scheduling heuristics with genetic programming for optimization of quality of service in weakly hard real-time systems

The weakly hard real-time system model is used for describing the real-time systems that allow occasional violations of real-time timing constraints. These systems include real-time control systems, multimedia systems, and communication systems. In some approaches that deal with mitigating the system overload in real-time systems with periodic tasks, namely job-skipping algorithms, the constraints defined by the weakly hard real-time model are used as a mechanism for defining the pattern of task instances (jobs) that may be skipped in order to reduce the system load. The performance of these algorithms is usually evaluated with respect to the quality of service metric, which depends on the number of skipped jobs. In this work, we investigate the possibility of using genetic programming in the automated synthesis of scheduling heuristics for optimizing skipping patterns in order to increase the average quality of service in comparison with the conventional job-skipping algorithms. Using genetic programming to automatically synthesize heuristics allows for an easy and quick design of novel heuristics for various problem types and optimization criteria. We present two different approaches for implementing the proposed method. The first approach is to encapsulate the evolved heuristics into job-skipping algorithms known from the literature, namely Red Tasks as Late as Possible (RLP) and Blue When Possible (BWP). The idea of the second approach is to employ the evolved heuristics as standalone job-skipping algorithms. The results show an improvement of up to 15% in comparison with the state-of-the-art algorithms. The novel methods described in this work present a significant upgrade of the standard job-skipping algorithms as they provide a notable improvement in terms of quality of service while ensuring the fulfillment of weakly hard constraints. Moreover, the presented methods are computationally efficient and are therefore suitable for implementation on real-time operating systems, which is not the case with similar methods based on optimization techniques.

IEEE TC Special Issue on Real-Time Systems

The fifteen papers in this special section focus on real-time systems. They present state-of-the-art work in theory, design, analysis, implementation, and evaluation of real-time systems. All the papers address some form of real-time requirements such as deadlines, response times or delays/latency and consider not only hard real-time systems but also time-sensitive systems in general. Following an open call for papers, authors from all over the globe sent 53 submissions on a broad range of topics. The review committee of top experts worldwide conducted rigorous professional reviews. Each paper at least 3 reviews in the first round. Approximately 50 reviews were performed in the second round to evaluate the revised submissions.

Optimized Scheduling of Periodic Hard Real-Time Multicore Systems

Multicore systems were developed to provide a substantial performance increase over monocore systems. But shared hardware resources are a problem as they add unpredictable delays that affect the schedulability of multicore hard real-time systems. In recent years much effort has been put into modelling interference and proposing scheduling techniques to mitigate its negative effect. Using one of these models, we propose a scheduling technique, based on Integer Linear Programming (ILP) that, in combination with a task to core allocator, not only achieves a feasible schedule but also reduces the interference produced by shared hardware resources in the context of hard real-time multicore systems. The evaluation shows how both the interference is reduced (≈ 83.47%) and the schedulability is increased (≈ 12.25%) compared to traditional heuristics.

Ethernet networks with deterministic delays

The work is devoted to a new technology that provides low and predictable data transmission delays in industrial Ethernet networks. The traffic is divided into critical and non-critical to delays. The features of TSN functioning are considered. The operating principle and architecture of such networks are considered. It is shown that cost reduction can be achieved by having only one network that meets the requirements of deterministic networking and is compatible with modern Ethernet solutions. Examples are given and it is shown that deterministic networks can be used to create hard real-time systems. This is especially true for automatic regulation and control systems that include feedback circuits. The key features of TSN that provide guaranteed message delivery times are traffic transmission time synchronization and scheduling. The TSN switch is presented as two subsystems, one of which performs standard Ethernet functions, and the second provides the TSN control logic. An example of cyclic traffic control according to the schedule is considered. The prospects of using TSN technology in industrial automation control networks are shown.

Hardware Debugging: an Overview of Modern Approaches

The ubiquity of complex devices built on systems on chip (SoC) with multiple processor cores poses new challenges for developers of embedded systems. New development tools specifically designed for complex systems on chip can help solve them, but these tools are usually limited by the functionality of debugging support tools. High-quality debugging support with advanced features is necessary to take full advantage of complex SoC devices while reducing development time. The article discusses various mechanisms and ways to implement support for debugging systems on chip designed for complex real-time systems used, for example, in the Internet of Things (IoT) paradigm. This review includes an assessment of the available solutions and their suitability for use with the next generation of complex systems on chip with multiple processor cores. It is shown that many existing solutions do not allow developers to easily take advantage of complex functions integrated into the next-generation SoC. The basic debugging support functions for multicore SoCs are summarized and discussed. Recommendations are given for SoC develo­pers and for the future direction of research in this area in order to provide a more suitable basis for new development tools. Such tools are extremely necessary for all embedded hard real-time systems and are of high importance for minimizing the complexity of their development. Modern systems and devices implementing the Internet of Things paradigm are increasingly required to have sufficiently high real-time performance while maintaining low power consumption. These requirements lead to the cre­ation of multicore SoC solutions with support for a wide range of peripheral devices and communication protocols. The systems are limited by the requirements for working in harsh conditions, such as, for example, in the engine compart­ment of a car or on a radar tower. The development of embedded hard real-time systems, in which a task that fails to be completed on time can lead to physical damage of the device, is a complex process. Effective tools, such as interactive debuggers and profilers, are an integral part of solving these problems and are vital for developing reliable embedded systems. Modern technologies now allow the integration of the entire system on a single silicon chip, known as a system on a chip (SoC), which leads to the relocation of existing external interfaces, widely used for development purposes, to the chip. Traditionally, communication within an embedded system is carried out using an external processor system bus, which is implemented in the form of tracks on a printed circuit board. The printed circuit board must support the appropriate interfaces of development tools that require a physical connection, such as, for example, logic analyzers and oscilloscopes. Previously, placing exter­nal interfaces on a chip left fewer options for external analysis tools and, in fact, makes developers "blind" to the internal state of the SoC. Without a reliable and consistent representation of the state of the embedded system, the detection of defects or errors in the system may become difficult or even impossible. The main solution to the problem of the lack of external interfaces is to provide access to internal nodes from outside the system through existing interfaces. There are many different approaches to achieving the required visibility, and they are outlined in this review.

Reducing the fault vulnerability of hard real-time systems

With the progress of the technology, the presence of transient faults (e.g. bit-flipping errors) in cache memories becomes a challenge, especially in embedded real-time systems. These are mission critical systems that are often subject to both fault-tolerant and real-time constraints.To reduce the impact of transient faults, hardware protection mechanisms are usually proposed. However, these mechanisms introduce too much pessimism in the computation of the worst-case execution time of a task, decreasing the overall system performance.In this paper, we propose a methodology to evaluate and reduce the vulnerability of hard real-time applications to soft errors in IL1 cache memories.We use static analysis tools to analyze a binary program and compute the overall vulnerability of its instructions. Then, we propose to reduce this vulnerability by invalidating some cache blocks at specific instants during the execution, thus forcing vulnerable instruction blocks to be reloaded from higher layers of memory. Since adding invalidation points will likely increase the WCETs of the tasks, we perform a static analysis to guarantee that the application deadlines are respectedFinally, we analyze how our methodology can be combined with hardware protection mechanisms as ECC memories, and we evaluate the performance on a set of benchmarks.

Improving Symbolic System-Level Synthesis by Solver Coordination and Domain-Specific Heuristics

Deciding binding, routing, and scheduling within system synthesis for hard real-time systems can be a challenging task. Symbolic methods leveraging results from the area of satisfiability modulo theories (SMT) solving have shown to be scalable methods for this by splitting the work between a logic solver for routing and binding, and a background theory solver performing schedulability analysis. For these methods, in order to prune the search space of infeasible implementations efficiently, a feedback by the background theory is required. It can be observed that previous approaches might fail here as feedback cannot be derived within a reasonable amount of time. We propose a coordinated synthesis approach that overcomes this issue. Here, we leverage an answer set solver as logic solver that is enhanced with a scheduling-aware binding and routing refinement. Based on the answer set solver’s decisions for binding and routing, a background theory solver then computes time-triggered schedules to resolve resource access conflicts. If no feasible schedule exists, a feedback to the answer set solver can be derived within reasonable time. Our experiments synthesizing massively parallel hardware architectures show that our approach increases the applicability of symbolic synthesis considerably. While more than half of the investigated instances in our experiments cannot be solved in the non-coordinated approach already at small 2-dimensional 3×3 tiled mesh hardware architectures with 60% average computational utilization per tile, the coordinated synthesis approach scales up to 5×5 architectures with average utilization of 70% per tile (2.8× the hardware architecture size than before). Furthermore, we increase the scalability and the robustness of our approach by encoding our domain-knowledge within domain-specific heuristics in our designated answer set solver. Within our experiments, we observe that the domain-specific heuristics enable us to scale up to 6×6 architectures with 70% average utilization per tile.

Interference-Aware Schedulability Analysis and Task Allocation for Multicore Hard Real-Time Systems

There has been a trend towards using multicore platforms for real-time embedded systems due to their high computing performance. In the scheduling of a multicore hard real-time system, there are interference delays due to contention of shared hardware resources. The main sources of interference are memory, cache memory, and the shared memory bus. These interferences are a great source of unpredictability and they are not always taken into account. Recent papers have proposed task models and schedulability algorithms to account for this interference delay. The aim of this paper is to provide a schedulability analysis for a task model that incorporates interference delay, for both fixed and dynamic priorities. We assume an implicit deadline task model. We rely on a task model where this interference is integrated in a general way, without depending on a specific type of hardware resource. There are similar approaches, but they consider fixed priorities. An allocation algorithm to minimise this interference (Imin) is also proposed and compared with existing allocators. The results show how Imin has the best rates in terms of percentages of schedulability and increased utilisation. In addition, Imin presents good results in terms of solution times.