Hard IP Research Articles

IC Floorplanning Optimization using Simulated Annealing with Order-based Representation

Integrated Circuits (IC) floorplanning is an important step in the integrated circuit physical design; it influences the area, wire-length, delay etc of an IC. In this paper, Order Based (OB) representation has been proposed for fixed outline floorplan with Simulated Annealing (SA) algorithm. To optimize the IC floorplan, two physical quantities have been considered such as area, and wire-length for hard IP modules. Optimization of the IC floorplan works in two phases. In the first phase, floorplans are constructed by proposed representation without any overlapping among the modules. In the second phase, Simulated Annealing algorithm explores the packing of all modules in floorplan to find better optimal performances i.e. area and wire-length. The Experimental results on Microelectronic Center of North Carolina benchmark circuits show that our proposed representation with SA algorithm performs better for area and wire-length optimization than the other methods. The results are compared with the solutions derived from other algorithms. The significance of this research work is improvement in optimized area and wire-length for modern IC.

Complicity of High-End SOC-FPGA’s for Data Centers

As the network traffic increasing significantly due to increase in Data streaming, Big Data Analytics, Cloud Computing, Increasing the load on Data Centers, Which leads to demand for high computational capabilities, low latency, high-bandwidth, power efficient data accelerators. As Re-Configurability of FPGA’s are more flexible for developing customized applications, so the FPGA hardware based data accelerators are the potential devices to achieve low latency and power efficient requirements. The modern FPGA’s are coming up with the embedded communication hard IP’s like PCIe, Ethernet, & DDR based memory controllers, which makes easy for the deployment of network attached FPGA’s in data centers. This paper presents the role of FPGA’s in datacenters and analysis of high-end FPGA’s by various vendors, which are suitable for deployment in data centers.

Core Communication Interface for FPGAs

The use of pre-designed and pre-verified hardware modules, also called IP cores, is an important part of the effort to design and implement complex systems. However, many aspects of IP core manipulation are still to be developed. This paper presents an approach to solve problems related to the dynamic interconnection of hard IP cores. The approach targets system-on-a-chip designs build in a single FPGA device. The paper proposes a communication interface that allows IP cores replacement during the FPGA normal operation. The same interface also allows the communication among distinct IP cores to take place.

Automated RTL Generator for Optimized Flop Repeater Network

In all Hard IP (HIP) designs, there is a need for signals to travel from its source to destination module. To meet timing, they are flop repeated based on the floorplan of the design. Different signals have unique repetition requirements based on their functionality/timing criticality. Also signals

Reconfigurable on-chip interconnection networks for high performance embedded SoC design

Abstract System on Chip (SoC) based embedded devices are providing key solutions to meet the demands of current and future high-performance embedded applications. These solutions become critical when the SoC IC designs are affected by the limitation of sub nanometer technologies that cannot be shrunk further. Network on Chip (NoC) is a scalable communication system that can provide efficient solutions for on-chip interconnection problems of SoCs such as re-configurability for multiple embedded applications. Most of the reconfigurable NoCs presented in the past improve performance of SoC at the expense of higher power and additional hardware. In this paper, we present a novel high-performance re-configurable NoC architecture that can improve the performance along with similar or improved power requirements of the system for different SoC applications. The proposed NoC architecture can also be considered as a hard IP for future partially configurable FPGA devices. Simulation and experimental results of our approach are compared with the recent on-chip interconnection approaches that supports our claim.

ASSESSMENT OF SHEAR BOND STRENGTH OF RESTORATIVE MATERIALS IN VARIOUS DEPTH OF HARD DENTAL TISSUE PREPARATION IN FRONT TEETH

In modern dentistry, there are two different approaches to the restoration of anatomy and aesthetics of anterior teeth. The most common is the option of direct restoration with using composite resin materials. The second option is the restoration with using ceramic materials that is carried out through the cooperation of the dentists and the dental laboratory technicians, or, alternatively, with various CAD-CAM systems directly at the dental office. This experiment was carried out by using teeth (premolars, incisors) without significant loss of hard dental tissues. Teeth with abrasion (all except 1st degree) were excluded from the test group. Within the framework of the planned study, the selected extracted teeth were prepared (a certain volume of hard tissues was removed from the vestibular side (a subgroup of the teeth prepared within in the enamel layer, and a subgroup of teeth with the exposed dentine). A total of 40 teeth were prepared (20 teeth with the exposed dentine, 20 with the enamel preparation). The tests were carried out by using a universal testing machine AUTOGRAPH AGS-J. A sample with a tooth was placed at the top of the device then the second part of the sample containing the plate of the material (composite or ceramic), was covered with the second part of the device to be tested, and neatly, trying to avoid applying tension to the adhesive butt joints, and then fastened to the lower clamping device of the tension testing machine. We created the shear forces before the sample was destroyed, paying attention to the character of adhesion line oddments. The results of the experiment have demonstrated that the most optimal shear strength is found out in the complex of hard tooth tissues and ceramic materials IPS Empress Aesthetic and EX3, in the teeth prepared within the tooth enamel layer. When using composite resin, the values studied are lower by 11,4% and 18,1%, (application of adhesion systems of 5th and 7th generations, respectively). In the cases when dentin is exposed, the shear strength decreases by 19,5% when using ceramics modified by leucite glass, by 17,3% in the case of application of feldspar ceramics, and by 8,4% and 13,2% for composite resin restoration when using adhesive systems of 5th and 7Ith generations respectively.

FPGA Implementation of RDMA-Based Data Acquisition System Over 100-Gb Ethernet

This paper presents an RDMA over Ethernet protocol used for data acquisition systems, currently under development at the ESRF. The protocol is implemented on Xilinx Ultrascale + FPGAs thanks to the 100G hard MAC IP. The proposed protocol is fairly compared with the well-known RoCE-V2 protocol using a commercial network adapter from Mellanox. Obtained results show the superiority of the proposed algorithm over RoCE-V2 in terms of data throughput. Performance tests on the 100G link show that it can reach a maximum stable link performance of 90 Gbps with minimum packets sizes greater than 1KB and 95Gbps for packet sizes greater than 32KB.

Regression based FPGA power estimation tool (FPE_Tool) for embedded multiplier block

Latest FPGA devices integrate processor, DSP blocks and memories as IP cores, due to which it is possible to build high performance FPGA based embedded applications. As all these hard and soft IP blocks are integrated on a single FPGA chip, the system consumes more power, which grows up at each new generation. Inside FPGA, embedded multiplier block is extensively used in the high performance design applications. Early estimation of power for this block provide evaluation to designer to design high performance and low power applications. In this paper a power estimation model has been developed for embedded multiplier block targeted to Spartan 3 FPGAs. The model is developed using regression and curve fitting approach. Several configurations of embedded multiplier having different I/O vector length are instantiated using Core Generator Tool and Xilinx Xpower Analyzer is used to compute leakage power and dynamic power.

LH-CAM: Logic-Based Higher Performance Binary CAM Architecture on FPGA

Binary content-addressable memory (BiCAM) is a popular high speed search engine in hardware, which provides output typically in one clock cycle. But speed of CAM comes at the cost of various disadvantages, such as high latency, low storage density, and low architectural scalability. In addition, field-programmable gate arrays (FPGAs), which are used in many applications because of its advantages, do not have hard IPs for CAM. Since FPGAs have embedded IPs for random-access memories (RAMs), several RAM-based CAM architectures on FPGAs are available in the literature. However, these architectures are especially targeted for ternary CAMs, not for BiCAMs; thus, the available RAM-based CAMs may not be fully beneficial for BiCAMs in terms of architectural design. Since modern FPGAs are enriched with logical resources, why not to configure them to design BiCAM on FPGA? This letter presents a logic-based high performance BiCAM architecture (LH-CAM) using Xilinx FPGA. The proposed CAM is composed of CAM words and associated comparators. A sample of LH-CAM of size ${64\times 36}$ is implemented on Xilinx Virtex-6 FPGA. Compared with the latest prior work, the proposed CAM is much simpler in architecture, storage efficient, reduces power consumption by 40.92%, and improves speed by 27.34%.

Approximating polyhedra with sparse inequalities

In this paper, we study how well one can approximate arbitrary polytopes using sparse inequalities. Our motivation comes from the use of sparse cutting-planes in mixed-integer programing (MIP) solvers, since they help in solving the linear programs encountered during branch-&-bound more efficiently. However, how well can we approximate the integer hull by just using sparse cutting-planes? In order to understand this question better, given a polyope $$P$$P (e.g. the integer hull of a MIP), let $$P^k$$Pk be its best approximation using cuts with at most k non-zero coefficients. We consider $${\text {d}}(P, P^k) = \max _{x \in P^k} \left( \min _{y \in P} \Vert x - y\Vert \right) $$d(P,Pk)=maxx?Pkminy?P?x-y? as a measure of the quality of sparse cuts.In our first result, we present general upper bounds on $${\text {d}}(P, P^k)$$d(P,Pk) which depend on the number of vertices in the polytope. Our bounds imply that if $$P$$P has polynomially many vertices, using half sparsity already approximates it very well. Second, we present a lower bound on $${\text {d}}(P, P^k)$$d(P,Pk) for random polytopes that show that the upper bounds are quite tight. Third, we show that for a class of hard packing IPs, sparse cutting-planes do not approximate the integer hull well, that is $$d(P, P^k)$$d(P,Pk) is large for such instances unless k is very close to n. Finally, we show that using sparse cutting-planes in extended formulations is at least as good as using them in the original polyhedron, and give an example where the former is actually much better.

Overview of Custom Microcontroller using Xilinx Zynq XC7Z020 FPGA

This paper presents an overview of customizable microcontroller using a Xilinx Zynq XC7Z020 FPGA as an alternative to increase its performance as user need. This alternative arises due to many of the systems, which developed mostly by using microcontroller are not giving any room for customization to increase its performance or I/O ports. There is any possibility that the system designed to be used by using general processor such as PC to increase its performance but it will give another problem such as interface difficulty for high speed I/O, real time processing, increases complexity, and many more. Customization is introduced by combining hard IP processor and FPGA in one chip instead of practicing two separate devices, processor and FPGA, which is commonly use in high performance embedded design. This approach allows seamless design development and development time reduction for customization.

Research Needs for TSV-Based 3D IC Architectural Floorplanning

This article presents key research needs in three-dimensional integrated circuit (3D IC) architectural floorplanning. Architectural floorplaning is done at a very early stage of 3D IC design process, where the goal is to quickly evaluate architectural designs described in register-transfer level (RTL) in terms of power, performance, and reliability. This evaluation is then fed back to architects for further improvement and/or modifications needed to meet the target constraints. We discuss the details of the following research needs in this article: block-level modeling, through-silicon-via (TSV) insertion and management, and chip/package co-evaluation. The goal of block-level modeling is to obtain physical, power, performance, and reliability information of architectural blocks. We then assemble the blocks into multiple tiers while connecting them using TSVs that are placed in between hard IPs and inside soft IPs. Once a full-stack 3D floorplanning is obtained, we evaluate it so that the feedback is provided back to architects.

A Cost-efficient Input Vector Monitoring Concurrent On-line BIST Scheme Based on Multilevel Decoding Logic

Input vector monitoring concurrent on-line BIST based on multilevel decoding logic is an attractive approach to reduce hardware overhead. In this paper, a novel optimization scheme is proposed for further reducing the hardware overhead of the decoding structure, which refers to improved decoding, input reduction, and simulated annealing inputs swapping approaches. Furthermore, utilizing similar multilevel decoding logic as the responses verifier, a novel cost-efficient input vector monitoring concurrent on-line BIST scheme is presented. The proposed scheme is applicable to the concurrent on-line testing for the CUT, the detail of which can not be obtained, such as hard IP cores. Experimental results indicate that the proposed optimization approaches can significantly reduce the hardware overhead of the decoding structure, and the proposed scheme costs lower hardware than other existing schemes.

A Resilient Authentication and Trojan Detection Technique for Hard IP

A manufacture-ready design layout of a chip is vulnerable to authentication threats and infection with trojan horse in its fabrication facility or in a SoC house. The existing countermeasures are sensitive to process variation. We propose a layout watermarking scheme through reorientation of few dummy fills in the interconnect layer and resizing of few net segments. Layout watermarking is so performed that it has a controlled delay effect on the active paths leading to certain scan flip-flops chosen judicially. This delay effect can be captured as delay fault induced responses from the packaged chip while tested with a faster clock and a particular test vector pair, but the difference of post-marking delay with respect to the test clock period remains more than the effect of process variation. Results on overhead of watermarking and its robustness for ISCAS’85 benchmark circuits are encouraging.

An Analog Front-End Circuit for ISO/IEC 14443-compatible RFID Interrogators

An analog front-end circuit for ISO/IEC 14443compatible radio frequency identification (RFID) interrogators was designed and fabricated by using a 0.25 µm double-poly CMOS process. The fabricated chip was operated using a 3.3 Volt single-voltage supply. The results of this work could be provided as reusable IPs in the form of hard or firm IPs for designing single-chip ISO/IEC 14443-compatible RFID interrogators.

Experience with a Hybrid Processor: K-Means Clustering

We discuss hardware/software co-processing on a hybrid processor for a compute- and data-intensive multispectral imaging algorithm, k-means clustering. The experiments are performed on two models of the Altera Excalibur board, the first using the soft IP core 32-bit NIOS 1.1 RISC processor, and the second with the hard IP core ARM processor. In our experiments, we compare performance of the sequential k-means algorithm with three different accelerated versions. We consider granularity and synchronization issues when mapping an algorithm to a hybrid processor. Our results show that speedup of 11.8X is achieved by migrating computation to the Excalibur ARM hardware/software as compared to software only on a Gigahertz Pentium III. Speedup on the Excalibur NIOS is limited by the communication cost of transferring data from external memory through the processor to the customized circuits. This limitation is overcome on the Excalibur ARM, in which dual-port memories, accessible to both the processor and configurable logic, have the biggest performance impact of all the techniques studied.