Handle Substrate Research Articles

Ultra-small high‐temperature pressure sensor chips fabricated in single‐layer (111) SOI wafers

This paper presents a 0.5 mm × 0.5 mm tiny-sized high-temperature piezoresistive pressure sensor fabricated with a thin-film under bulk single-sided micromachining process from the front-side of single-layer (111) silicon on insulator (SOI) wafer. The (111)-device layer of the SOI wafer is specifically selected to optimize the piezoresistor performance where the SiO2 buried layer isolates the piezoresistors from the handle substrate. And the (111)-handle layer is employed to subtly construct a single-crystalline-silicon beam-island combining with a very thin but uniform poly-silicon diaphragm for realization of both low nonlinearity and high sensitivity. Without double-sided micromachining process and wafer bonding used, a tiny sensor-chip size of 0.5 mm × 0.5 mm is achieved, which is required in wind-tunnel systems for measuring pressure distribution at high temperature. The testing results of the fabricated sensor show high sensitivity of 0.15 mV V−1 kPa−1 for 150 kPa measure range and satisfactory linearity of ±0.11% FS (full scale) at ambient temperature. At 350 °C, the overall accuracy is 0.17% FS and the thermal hysteresis is 0.22% FS. The temperature coefficient of zero-point offset of the sensor is tested as low as 0.01% °C−1 FS and the temperature coefficient of sensitivity is −0.07% °C−1 FS within the whole temperature range from −55 °C to 350 °C. Featuring the advantages of high accuracy and high-yield low-cost fabrication, the tiny-sized high-temperature pressure sensors exhibit promising perspectives in the field of aerospace industry including wind-tunnel applications.

Integrating GeSn photodiode on a 200 mm Ge-on-insulator photonics platform with Ge CMOS devices for advanced OEIC operating at 2 μm band.

High-performance GeSn multiple-quantum-well (MQW) photodiode is demonstrated on a 200 mm Ge-on-insulator (GeOI) photonics platform for the first time. Both GeSn MQW active layer stack and Ge layer (top Ge layer of GeOI after bonding) were grown using a single epitaxy step on a standard (001)-oriented Si substrate (donor wafer) using a reduced pressure chemical vapor deposition (RPCVD). Direct wafer bonding and layer transfer technique were then employed to transfer the GeSn MQW device layers and Ge layer to a 200 mm SiO2-terminated Si handle substrate. The surface illuminated GeSn MQW photodiode realized on this platform exhibits an ultra-low leakage current density of 25 mA/cm2 at room temperature and an enhanced photo sensitivity at 2 μm of 30 mA/W as compared to a GeSn MQW photodiode on Si at 2 μm. The underlying GeOI platform enables monolithic integration of a complete suite of photonics devices operating at 2 μm band, including GeOI strip waveguides, grating couplers, micro-ring modulators, Mach-Zehnder interferometer modulators, etc. In addition, Ge CMOS circuits can also be realized on this common platform using a "photonic-first and electronic-last" processing approach. In this work, as prototype demonstration, both Ge p- and n-channel fin field-effect transistors (FinFETs) were realized on GeOI simultaneously with decent static electrical characteristics. Subthreshold swings of 150 and 99 mV/decade at |VD| = 0.1 V and drive currents of 91 and 10.3 μA/μm at |VG-VTH| = 1 V and |VD| = 0.75 V were achieved for p- and n-FinFETs, respectively. This works illustrates the potential of integrating GeSn (as photo detection material) on GeOI platform for Ge-based optoelectronics integrated circuits (OEICs) targeting communication applications at 2 μm band.

Annihilating Pores in the Desired Layer of a Porous Silicon Bilayer with Different Porosities for Layer Transfer

A silicon layer that is tens of micrometers thick on a handle substrate is desired for applications involving power devices, microelectromechanical systems (MEMS), highly efficient silicon solar cells (<50 µm), etc. In general, if the initial silicon layer obtained from the layer transfer process using the etch-stop or ion-cut techniques, which may provide very accurate thickness control, is too thin, then additional epitaxial growth is required to increase the thickness of the silicon layer. However, epitaxial growth under strict predeposition conditions is a time-consuming and expensive process. On the other hand, producing porous silicon via anodization in a hydrofluoric acid solution offers an efficient way to control the dimensions of the generated pores directly on the nano- or macroscale via the current density. When sintering the porous layer via high-temperature argon annealing, the porosity of the porous layer determines whether this porous layer can serve as a device layer or a separation layer. In addition, it is clearly easier to create a transferred layer ten of micrometers thick via anodization than by ion implantation and/or epitaxial deposition.

(Invited) SOI Technologies for RF and Millimeter Wave Applications

Silicon-on-Insulator (SOI) technology has taken the radio-frequency (RF) world by storm in the past decade. By offering high performance at low cost it has steadily displaced Gallium-Arsenide (GaAs) and Silicon-on-Sapphire (SOS) technologies to become the mainstream technology for implementing the RF switch banks in mobile applications. Indeed, in 2008 RF SOI accounted for less than 10% of switching modules in handsets, and today virtually 100% of all modern day smartphones include RF switches implemented in Partially Depleted SOI (PD SOI) on engineered and optimized trap-rich (TR) silicon based substrates. The huge success of current PD SOI (130 nm) in today’s RF market is due to significant technological improvements. First, the analog and high-frequency characteristics of the front-end of line (FEOL) active devices, i.e. advances at the transistor level, are presented, and second, the quality of the back-end of line (BEOL) process is reviewed. The BEOL encompasses the metals, dielectric layers and semiconductor substrate of the manufacturing process. Substantial losses arise in silicon substrates at RF frequencies due to the conductive nature of silicon, and simply reducing the nominal doping of the handle wafer is insufficient, as a parasitic conduction channel is induced by (even low-level) parasitic charged defects present at all silicon/insulator interface. This effect -and ways to counter it- are described in depth as it is responsible for large amounts of RF losses, parasitic coupling and high levels of non-linear signal distortion. In terms of CMOS FEOL, the RF characteristics of SOI devices are compared with those of other high-frequency technologies. It is shown that though SOI devices provide attractive RF performances, these alone do not account for SOI’s dominance in the silicon RF market (over technologies such as planar bulk or FinFETs). Indeed, on top of boasting high figures of merit (FoM) for RF applications, SOI technology owes its success to a unique compatibility with a passivation layer rich in traps that disables the aforementioned parasitic conduction channel below the buried oxide (BOX). The so called “trap-rich” substrates, that are composed of a high-defect polysilicon layer between the BOX and the high-resistivity silicon handle substrate, are virtually lossless and highly linear and are truly optimized for RF ICs. A variety of essential RF passive elements (inductors, transmission lines, filters, antennas, etc.) are presented that benefit strongly from trap-rich silicon-substrate’s properties, along with its beneficial impact on the key RF switching modules. The future trends of SOI are then addressed. A summary is made on the progress of the most advanced PD SOI nodes (65 and 45 nm) as well as the ultra-advanced Fully Depleted SOI (FD SOI) nodes (22 and 28 nm) that are demonstrating their potential for all kinds of RF and millimeter wave front-end circuit modules, such as low-noise amplifiers (LNAs), voltage controlled oscillators (VCOs), mixers, etc. From these results SOI is expected to be a big contender as a technological platform to enable mass production of 5G and IoT devices and products in the very near future. Finally, compatibility issues between advances FD SOI nodes and the trap-rich layer are discussed, and alternative silicon-based substrate solutions to overcome the problematic parasitic conduction channel are presented, such as porosification of the silicon handle, deep trap implantations, and smart PN doping patterns to fight against the unwanted conductive channel that degrades substrate RF performance, the latter technique being compatible with not only SOI but also with planar bulk technology.

Observational and theoretical validation of longitudinal type surface acoustic wave devices

The authors have proposed longitudinal type surface acoustic wave (SAW) devices comprising a LiNbO3 thin plate, acoustic mirror, handle substrate and interdigital transducers (IDT). This paper describes the observational and theoretical validation of the proposed devices by using a laser probe system and finite element analysis (FEA). It is shown that the laser probe system based on the Sagnac interferometer is effective for direct observation of the devices operated at even 2 GHz range through the observation of SAW field distribution of the existence and lack of acoustic mirror, their comparison with FEA results and changes of the transverse mode pattern. In addition, a phenomenon of SAW radiation normal to the busbars from IDT is found both observationally and theoretically, and a possible radiation mechanism explaining the results is also discussed.

(Invited) Current Status and Trends in RF Silicon-on-Insulator Material and Device

Performance of RF integrated circuit (IC) is directly linked to the analog and high frequency characteristics of the transistors, the quality of the back-end of line process as well as the electromagnetic properties of the substrate. This last decade Silicon-on-Insulator (SOI) MOSFET technology has demonstrated its potentialities for high frequency commercial applications pushing the limits of CMOS technology. Partially depleted SOI MOSFET is now the mainstream technology adopted by all major foundries and fabless companies for the design of several wireless sub-systems. Today, more than 95 percent of substrates used in fabricating cellular and connectivity switches for handsets are SOI (from Navian market analyst, 2016 report) whereas it was not even in production in 2008, GaAs being mainstream at that time. Beside main switch, front-end module complexity has increased drastically: more than ten integrated switches are required in 4G Tier 1 phones, plus antenna tuners as well as Low Noise Amplifiers (LNA). RF-SOI Power Amplifiers (PA) market adoption is slowly ongoing being mainly position on entry market favoring price-performance-integration trade-off. The concept of trap-rich SOI substrate proposed in 2005 is at the origin of the RF-SOI success story. Indeed, substrate losses and crosstalk were the remaining killer features of Si-based technologies for RF applications these last decades. Thanks to the introduction of a high density of defects called traps at the buried oxide (BOX) / Si handle substrate interface, it has been possible to manufacture high-resistivity (HR) SOI substrates characterized with an effective resistivity as high as 10 kΩ.cm. Those traps originate from the grain boundaries in a thin (less than 1 µm-thick) polysilicon layer. This high-resistivity characteristic, which is conserved after a full CMOS process, translates to very low RF insertion loss (< 0.15 dB/mm at 1 GHz) along coplanar waveguide (CPW) transmission lines and purely capacitive crosstalk similarly to quartz substrate. It has been shown that the presence of a trapping layer does not alter the DC or RF behavior of SOI MOS transistors. And more importantly, it has been demonstrated that harmonics level originated from the substrate is reduced by at least 20 dB moving from standard resistivity SOI substrate (~ 10 Ω.cm) to high resistivity SOI (~ 1 kΩ.cm), and an additional drop of 40 dB is achieved with the innovative trap-rich HR SOI substrate. The low harmonic level achieved is comparable with insulating substrate. The improvement of the HR SOI substrate with the introduction of defects brings also clear benefits for the integration of passives, such as the quality factor of spiral inductors, tunable MEMS (microelectromechanical systems) capacitors, as well as for the reduction of the substrate noise (crosstalk) between devices integrated on the same chip, etc. Université catholique de Louvain and Soitec have been working together to manufacture the trap-rich SOI substrate concept to further improve the high-frequency performance of commercially available HR-SOI substrates. In 2013, Soitec has unveiled a new flavor of HR-SOI called RF-eSITM-SOI, for enhanced Signal IntegrityTM substrate with a measured effective resistivity as high as 10 kΩ.cm. RF-eSI-SOI substrate can really be considered as a lossless Si-based substrate. Beyond switch, RF-eSI-SOI technology opens the path to further system integration in the Front-End Module (FEM) space as well as even more complex mixed signal System-on-Chip. Based on its 45 nm baseline SOI process, GlobalFoundries just released a RF-SOI mmW offering targeting applications like 5G, satellite communication, automotive radar, WiGig, backhaul. The SOI substrates roadmap for RF and millimeter-waves applications will be presented. Future generations of mobile communication systems such as 5G or the Internet-of-Things will require transistors with better high frequency performance at lower power consumption. The advanced MOS transistors in competition are FinFET and Ultra Thin Body and Buried oxide (UTBB) SOI MOSFETs. Both devices have been intensively studied these last years. Most of the reported data concern their digital performance. Their analog/RF behavior will be described and compared in the paper. Both show pretty similar characteristics in terms of transconductance, Early voltage, voltage gain, self-heating issue but UTBB outperforms FinFET in terms of cutoff frequencies thanks to their relatively lower fringing parasitic capacitances. The relative impact of the transistor characteristics and the substrate properties on different RF ICs performances will be presented. As it will be demonstrated, the use of specific RF test structures at the early stage of a technological node development is of first importance to analyze the transistor parasitic resistances and capacitances, the transistor cutoff frequencies, the self-heating, and the substrate coupling and non-linear behavior.

GaAs p-i-n Photodiode Array on GaP Using Wafer Fusion

In this letter, we describe a novel wafer fusion process for transferring GaAs p-i-n junctions onto a GaP handle substrate. A process for patterning large arrays (30×30) of these photodiodes using a wet etch scheme is presented. We also present photoresponse characteristics of these diodes both with and without the high temperature wafer fusion process. Application of this device in an optically addressed adaptive optics system is also discussed.

160 MILLI-OHM ELECTRICAL RESISTANCE THRU-WAFER INTERCONNECTS WITH 10:1 ASPECT RATIO

We present a novel approach for high-aspect ratio low resistance Thru-Wafer Interconnects for Double-Sided (TWIDS) fabrication of MicroElectroMechanical Systems (MEMS). The interconnects are formed by etching blind via holes in the handle substrate of an SOI (Silicon on Insulator) wafer, followed by filling the holes with copper, using sonic-assisted seedless copper electroplating process. This technique does not require additional conductive layer deposition, but utilizes a highly doped silicon device layer as a seed. The donut-shape gaps are etched around the copper filled vias to provide interconnects insulation. We introduced the fabrication process and characterized the performance of interconnects. Experimental analysis of an array of 22 interconnects demonstrated that the resistance values as low as 160 milli-Ohm can be achieved. Parasitic capacitance of interconnects is analytically calculated and the distortion of the MEMS resonator transduction spectrum is predicted using an equivalent circuit model. Signal amplitude and phase distortion due to the parasitic capacitance are estimated to be 1.15 dB and 5.96 deg, respectively, for the optimum 60 um diameter via with 35 um insulating gap. The method presented is compatible with an in-house folded MEMS fabrication process and may enable 3D folded TIMU (Timing Inertial Measurement Unit) structures with thru-wafer interconnects.

BULK ACOUSTIC WAVE GYROSCOPE

Capacitive bulk acoustic wave x, y and z-axes gyroscopes implemented on (100) and (111) silicon substrates are disclosed. Exemplary gyroscopes comprise a handle substrate, a bulk acoustic wave resonator element supported by the handle substrate, and a plurality of electrodes surrounding and separated from the resonator element by very small capacitive gaps. The electrodes can excite and detect at least two degenerate bulk acoustic wave resonant modes in the resonator. Advantages include reduced size; higher Q, which improves noise and bias stability; larger bandwidth, and improved shock resistance. In addition, the high Q is maintained in atmospheric or near-atmospheric pressure which reduces the cost and complexity of the wafer-scale packaging of the gyroscope.

Monolithic integration of silicon CMOS and GaN transistors in a current mirror circuit

GaN high electron mobility transistors (HEMTs) were monolithically integrated with silicon CMOS to create a functional current mirror circuit. The integrated circuit was fabricated on 100 mm diameter modified silicon-on-insulator (SOI) wafers incorporating a resistive (111) silicon handle substrate and a lightly doped (100) silicon device layer. In a CMOS-first process, the CMOS was fabricated using the (100) device layer. Subsequently GaN was grown by plasma molecular beam epitaxy in windows on the (111) handle substrate surface without wire growth despite using gallium-rich growth conditions. Transmission lines fabricated on the GaN buffer/SOI wafer exhibited a microwave loss of less than 0.2 dB/mm up to 35 GHz. Direct current measurements on GaN HEMTs yielded a current density of 1.0 A/mm and transconductance of 270 mS/mm. At 10 GHz and a drain bias of 28 V, 1.25 mm long transistors demonstrated a small signal gain of 10.7 dB and a maximum power added efficiency of 53% with a concomitant power of 5.6 W. The silicon and GaN transistors were interconnected to form high yield test interconnect daisy chains and a monolithic current mirror circuit. The CMOS output drain current controlled the GaN transistor quiescent current and consequently the microwave gain.

Flexible In-plane Photonic Devices Based on Transferrable Si Nanomembranes on Polyimide Film

The flexible electronics and photonics have attracted a lot of attentions in past decade because of their potentially wide applications. A general method to fabricate nanomembrane flexible device involves two steps. At first, a nanomembrane on top of a sacrificial layer is patterned. Then, the nanomembrane is freed by high selective etching of the sacrificial layer and then weakly bonds to the handle substrate by Vander Waals forces. Later on, the released devices are transferred to the target flexible substrates. Notable successes include paper-like display, flexible silicon integrated circuits, photonic crystal filter and sensor skins, and so on. However, the progress in flexible photonic device is still limited to surface-normal devices such as photonic crystal filter. This type of devices usually has a large area and/or same dimensions which makes the transfer much easier than in-plane photonic device. This paper reports the transfer of in-plane Silicon nanomembrane photonic devices on polyimide flexible film. Employing a slightly modified transfer process, passive optical components, such as optical waveguide and multimode multimode interferometer, are successfully transferred on to Kapton polyimide film.

Fabrication of GaAs-on-Insulator via Low Temperature Wafer Bonding and Sacrificial Etching of Ge by XeF2

Front end integration of III-V compound semiconductor devices with Si complimentary metal-oxide-semiconductor (CMOS) technology requires the development of commercially viable engineered substrates. The fabrication of engineered substrates currently utilizes technologies such as epitaxy, wafer bonding and layer exfoliation. In this paper we report on the development of GaAs-on-insulator (GaAsOI) structures without the use of Smart Cut technology. Epitaxial GaAs/Ge/GaAs stacks containing an embedded Ge sacrificial release layer were grown with metal-organic chemical vapor deposition (MOCVD) and exhibit both a low defect density as well as surface properties suitable for wafer bonding. A room temperature oxide-oxide bonding process was developed to enable the integration of substrates with a large difference in their coefficients of thermal expansion. The release of the donor substrate and transfer of the GaAs layer onto the handle substrate was realized through room temperature, gas-phase lateral etching of the embedded Ge sacrificial layer by exposure to xenon difluoride (XeF2). This GaAsOI fabrication process is shown to be successful on a small scale, though implementation for the production of commercially-viable large area GaAsOI substrates at full wafer scale is currently limited by the long gas transport distance associated with a wafer-scale lateral etching process. In order to explore possibilities for overcoming this limitation we established a model that identifies the rate limiting processes and discuss potential approaches that will allow for the implementation of our gas phase lateral etching process for the fabrication of large diameter GaAsOI substrates.

Pattern Dependence of Epitaxial-Realignment in Direct Silicon Bonded (DSB) Substrates with Hybrid Crystal Orientation

Direct Silicon Bonded Si (DSB) technology with amorphization templated recrystallization process enables a relatively simple integration of CMOSFET using hybrid orientation bulk substrates. The absence of oxide at the bonding interface enables the change of the orientation of the donor Si film to that of the handle substrate after amorphization and recrystallzation. Therefore, an epitaxial realignment is caused by the absence of oxide at the bonding interface during the high-temperature annealing for recrystallzation. This paper describes the issues concerning the epitaxial realignment of DSB hybrid orientation bulk substrates, focusing on the pattern structure and rotation angle of donor layer and handle wafer dependence.

Fabrication of Transfer-Enhanced Semiconductor Substrates by Wafer Bonding and Hydrogen Exfoliation Techniques

A transfer-enhanced semiconductor substrate has been demonstrated, integrating a thin InP layer on a Si handle substrate with an imbedded porous silicon layer. A Si wafer was anodized to create a low-density porous surface layer. A thin layer of InP was transferred to the Si handle substrate through wafer bonding and hydrogen-induced exfoliation. High-resolution X-ray diffraction, atomic force microscopy, and transmission electron microscopy characterization showed the structure to have high surface and crystalline quality for epitaxial deposition after undergoing chemical mechanical polishing. Layer transfer capability was demonstrated with a similar structure by mechanical fracture through the porous Si layer.

Structure of elastically strain-sharing silicon(110) nanomembranes

Nanomembranes composed of single-crystal, tensilely strained Si(110) and compressively strained SiGe(110) layers have been fabricated from silicon-on-insulator (SOI) substrates. Elastic strain sharing is demonstrated for a trilayer structure consisting of a 12 nm Si/80 nm Si0.91Ge0.09 film epitaxially grown on a 12 nm thick (110) oriented Si template layer that is subsequently released from its handle substrate. X-ray diffraction on the as-grown and released structures confirms a virtually dislocation-free membrane with a tensile strain of 0.23±0.02% in the Si(110) layers after release. Lower growth temperatures in molecular beam epitaxy allow for smoother growth fronts than are possible using chemical vapour deposition.

Role of hydrogen in hydrogen-induced layer exfoliation of germanium

The role of hydrogen in the exfoliation of Ge is studied using cross-sectional transmission electron microscopy, atomic force microscopy, and multiple-internal transmission mode Fourier-transform infrared absorption spectroscopy and compared with the mechanism in silicon. A qualitative model for the physical and chemical action of hydrogen in the exfoliation of these materials is presented, in which H-implantation creates damage states that store hydrogen and create nucleation sites for the formation of micro-cracks. These micro-cracks are chemically stabilized by hydrogen passivation, and upon annealing serve as collection points for molecular hydrogen. Upon further heating, the molecular hydrogen trapped in these cracks exerts pressure on the internal surfaces causing the cracks to extend and coalesce. When this process occurs in the presence of a handle substrate that provides rigidity to the thin film, the coalescence of these cracks leads to cooperative thin film exfoliation. In addition to clarifying the mechanism of H-induced exfoliation of single-crystal thin Ge films, the vibrational study helps to identify the states of hydrogen in heavily damaged Ge. Such information has practical importance for the optimization of H-induced layer transfer as a technological tool for materials integration with these materials systems.

Si layer transfer to InP substrate using low-temperature wafer bonding

Using a low-temperature wafer bonding process, InP substrates are bonded to silicon-on-insulator (SOI) substrates at 220 °C. A combination of oxygen plasma and chemical treatment results in a direct contact bonding at room temperature. After the bonding process at 220 °C for 45 min, removal of the Si handle substrate by sacrificial etching of the buried oxide layer in SOI, results in a thin membrane of Si robustly bonded to InP. The thin Si membrane bonded to InP shows uniformly bonded interface under high-resolution electron microscopy. Micro-Raman analysis has also been carried out to study the bonded interface. I– V characteristics of the bonded structures suggest that such bonding and layer transfer processes are suitable for device integration.

Strain evolution in hydrogen-implanted silicon

The structural changes that accommodate wafer splitting after hydrogen implantation of silicon and the transfer of split layers to a handle substrate were investigated using triple axis x-ray diffraction, to monitor the strain in the implanted layer, and atomic force microscopy. Silicon substrates (004) were implanted with a hydrogen dose that ranged from 5×1015 cm−2 to 8×1016 cm−2 and energies of either 30 kV or 140 kV. The changes in the implanted layer properties were investigated after annealing at 150–300°C for short times. For annealing temperatures up to 150°C, the strain-induced implant profile did not change appreciably nor did the surface roughness increase, indicating that, for these implant conditions, the implant is stable. Annealing at 200°C or higher for 10 min or more led to increased surface roughness and a change to the implant profile, although blister formation did not occur. Higher surface roughness is not conducive to successful wafer bonding, so these measurements helped to determine the annealing sequence that is appropriate for bonding. In this case, hydrophobic bonded wafers were successfully fabricated with the transferred layer showing similar structural properties as a thin epitaxial film of the same thickness. The use of x-ray scattering for this technique can be easily transferred to other materials for which other techniques, such as infrared absorption, have not been developed.

Polycrystalline silicon layer transfer by ion-cut

Ion-cut polycrystalline silicon (polysilicon) layer transfer by thermal separation was demonstrated after observing hydrogen-induced surface blistering and direct bonding of a chemomechanically polished surface. After hydrogen implantation into a chemical-vapor deposited polysilicon wafer (the donor wafer), the wafer surface was polished for wafer bonding. The hydrogen-implanted and polished wafer was then bonded to a thermally oxidized silicon wafer (the handle wafer) by low-temperature wafer direct bonding. The bonded pair was then heated until hydrogen-induced silicon layer cleavage occurred along the hydrogen-implanted layer, resulting in the transfer of the polysilicon layer to the handle substrate. The transferred polysilicon surface had the same roughness as ion-cut single-crystal silicon layers. The layer transfer time of polysilicon was significantly reduced from that of single-crystal silicon, and had an activation energy nearly ten times lower than that of its single-crystal counterpart.

High-resolution x-ray diffraction for characterization and monitoring of silicon-on-insulator fabrication processes

High-resolution x-ray diffraction (HRXRD) was used to monitor silicon-on-insulator (SOI) device fabrication processes. The use of HRXRD is attractive since it is nondestructive and can be applied directly to product wafers. We show the usefulness of this technique for the characterization of amorphizing implants for shallow junctions, solid phase recrystallization of implanted junctions, cobalt-silicide formation, and oxidation; all are critical processes for complementary metal oxide semiconductor device fabrication on SOI. We also found the technique applicable to multilayered SOI structures fabricated by wafer bonding, where the tilt and rotation of each SOI layer with respect to the handle substrate, allowed us to obtain independent measurements of each SOI film.