160 MILLI-OHM ELECTRICAL RESISTANCE THRU-WAFER INTERCONNECTS WITH 10:1 ASPECT RATIO

Abstract

We present a novel approach for high-aspect ratio low resistance Thru-Wafer Interconnects for Double-Sided (TWIDS) fabrication of MicroElectroMechanical Systems (MEMS). The interconnects are formed by etching blind via holes in the handle substrate of an SOI (Silicon on Insulator) wafer, followed by filling the holes with copper, using sonic-assisted seedless copper electroplating process. This technique does not require additional conductive layer deposition, but utilizes a highly doped silicon device layer as a seed. The donut-shape gaps are etched around the copper filled vias to provide interconnects insulation. We introduced the fabrication process and characterized the performance of interconnects. Experimental analysis of an array of 22 interconnects demonstrated that the resistance values as low as 160 milli-Ohm can be achieved. Parasitic capacitance of interconnects is analytically calculated and the distortion of the MEMS resonator transduction spectrum is predicted using an equivalent circuit model. Signal amplitude and phase distortion due to the parasitic capacitance are estimated to be 1.15 dB and 5.96 deg, respectively, for the optimum 60 um diameter via with 35 um insulating gap. The method presented is compatible with an in-house folded MEMS fabrication process and may enable 3D folded TIMU (Timing Inertial Measurement Unit) structures with thru-wafer interconnects.