Guard Ring Width Research Articles

Study of the influence of virtual guard ring width on the performance of SPAD detectors in 180 nm standard CMOS technology

The influence of the virtual guard ring width (GRW) on the performance of the p-well/deep n-well single-photon avalanche diode (SPAD) in a 180 nm standard CMOS process was investigated. TCAD simulation demonstrates that the electric field strength and current density in the guard ring are obviously enhanced when GRW is decreased to 1 μm. It is experimentally found that, compared with an SPAD with GRW = 2 μm, the dark count rate (DCR) and afterpulsing probability (AP) of the SPAD with GRW = 1 μm is significantly increased by 2.7 times and twofold, respectively, meanwhile, its photon detection probability (PDP) is saturated and hard to be promoted at over 2 V excess bias voltage. Although the fill factor (FF) can be enlarged by reducing GRW, the dark noise of devices is negatively affected due to the enhanced trap-assisted tunneling (TAT) effect in the 1 μm guard ring region. By comparison, the SPAD with GRW = 2 μm can achieve a better trade-off between the FF and noise performance. Our study provides a design guideline for guard rings to realize a low-noise SPAD for large-array applications.

Simulation of Silicon Surface Barrier Detector with PN Junction Guard Rings to Improve the Breakdown Voltage.

Silicon surface barrier detectors (SSBDs) are normally used to detect high-energy particles due to their excellent properties. For better charge collection efficiency (CCE), the SSBD device should be operated at higher reverse voltages, but this can lead to device breakdown. Therefore, we used a PN junction as a guard ring to increase the breakdown voltage of the SSBD. The structures of two SSBD devices are drawn and simulated in this work. Compared with a conventional SSBD (c-SSBD), the use of a PN junction as a guard ring for an SSBD (Hybrid-SSBD) achieves higher breakdown voltages, of over 1500 V under reverse bias. This means that Hybrid-SSBD devices can operate at higher reverse voltages for better charge collection efficiency (CCE) to detect high-energy particles. Then, we simulated the different structure parameters of the Hybrid-SSBD guard rings. Among them, the doping depth and gap width of the guard ring (between the innermost guard ring and the active area) have a greater impact on the breakdown voltage. Finally, for Hybrid-SSBD devices, the optimal characteristics of the guard ring were 1 × 1019 cm-3 doping concentration, 1 μm doping depth, and innermost guard ring width and gap width of 5 μm and 3 μm, respectively.

Research on the leakage current at sidewall of mesa Ge/Si avalanche photodiode

The effects of surface defects at the sidewall of absorption and multiplication layers on the sidewall leakage current in separate-absorption-charge-multiplication Ge/Si avalanche photodiodes with a mesa structure are investigated. It is found that high-density surface defects and a strong electric field at the sidewall are the reasons for the large sidewall leakage current. In addition, the influence of the width of the guard ring on the sidewall leakage current is also studied. It is found that increasing the width of the guard ring is beneficial to the reduction of the sidewall leakage current by reducing the sidewall electric field and the reduction is not significant when the guard-ring width is greater than 2 µm.

Design of High-Efficiency SPADs for LiDAR Applications in 110nm CIS Technology

Single photon avalanche diodes (SPADs) featuring a high detection rate of near-IR photons are much desired for outdoor LiDAR based on direct time-of-flight (ToF). This article presents the complete design flow of a SPAD detector for LiDAR. First, the selection of the emitter wavelength is discussed, considering the maximum allowed power underlying eye safety regulations, solar irradiance, and reflected signal power. Then, the choice of the SPAD structure is discussed based on the TCAD simulation of quantum efficiency and crosstalk. Next, the proposed P-well/ Deep N-well SPAD is explained. The electro-optical characterization of the detectors is presented as well. The performance of the time-of-flight image sensors is determined by the characteristics of the individual SPADs. To fully characterize this technology, devices with various sizes, shapes, and guard ring widths have been fabricated and tested. The measured mean breakdown voltage is 18 V. The proposed structure has a 0.4 Hz/μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> dark count rate and 0.5% afterpulsing. The FWHM (total) jitter and photon detection probability at 850nm wavelength are of 92 ps and 10%. All figures have been measured at 3 V excess voltage. Finally, the performance of the SPAD detector is analyzed by evaluating the signal-to-noise ratio at different acquisition times. Distance ranging measurements have been performed, achieving a depth resolution of 1 cm up to 6.3 m range.

The Effect of a Deep Virtual Guard Ring on the Device Characteristics of Silicon Single Photon Avalanche Diodes

Silicon single-photon avalanche diodes (Si-SPADs) fabricated with standard CMOS technology and providing the advantages of low noise, low cost, and compatibility with additional circuits are promising candidates for single-photon detection fields. The guard ring is a key component of SPADs, which prevents premature edge breakdown and improves the electric field distribution to the intended multiplication region. The choice of proper physical dimensions, especially the active radius (AR) and the size of the guard ring, is important for the better performance of Si-SPADs. In this paper, a Si-SPAD with a deep virtual guard ring fabricated through deep well diffusion is proposed and the effect of the physical variation of the AR and guard ring width on the device characteristics is investigated. In addition, the effect of physical variation on the device characteristics is analyzed and explained by means of technology computer-aided design (TCAD) simulations.

Cross-talk characterization of dense single-photon avalanche diode arrays in CMOS 150-nm technology

Cross-talk characterization results of high-fill-factor single-photon avalanche diode (SPAD) arrays in CMOS 150-nm technology are reported and discussed. Three different SPAD structures were designed with two different sizes (15.6 and 25.6 μm pitch) and three guard ring widths (0.6, 1.1, and 1.6 μm). Each SPAD was implemented in an array, composed of 25 (5×5) devices, which can be separately activated. Measurement results show that the average cross-talk probability is well below 1% for the shallow-junction SPAD structure with 15.6 μm pitch and 39.9% fill factor, and 1.45% for the structure with 25.6 μm pitch and 60.6% fill factor. An increase of cross-talk probability with the excess bias voltage is observed.

Optimization of Guard Ring Structures to Improve Latchup Immunity in an 18 V DDDMOS Process

The optimization of guard ring structures to improve latchup immunity in an 18 V double-diffused drain MOS (DDDMOS) process with the DDDMOS transistors has together been investigated in a silicon test chip. The layout parameters including the anode-to-cathode spacing and the guard ring width are also studied to seek their impacts on latchup immunity. The measurement results demonstrated that the test devices isolated with the specific guard ring structure of n-buried layer can highly improve the latchup immunity. The suggested guard ring structures can be applied to the high-voltage circuits in this 18 V DDDMOS process to meet the new Joint Electron Device Engineering Council standard (JESD78D) with the trigger current of over ±200 mA.

Crosstalk Characterization of Single-photon Avalanche Diode (SPAD) Arrays in CMOS 150nm Technology

In this paper, crosstalk characterization results of single-photon avalanche diode (SPAD) arrays in CMOS 150 nm technology are reported and discussed. SPADs are implemented in two different sizes (15.6 and 25.6 μm pitch) and three guard ring widths (0.6, 1.1 and1.6 μm). A SPAD array is composed of 25 (5×5) devices, which can be separately activated. Measurement results show that total crosstalk probability is well below 1% for arrays with conservative guard ring SPADs, and decreases with distance between devices. We also observed crosstalk is dependent on geometry parameters of SPADs.

Replacement correction factors for plane‐parallel ion chambers in electron beams

Plane-parallel chambers are recommended by dosimetry protocols for measurements in (especially low-energy) electron beams. In dosimetry protocols, the replacement correction factor P(repl) is assumed unity for "well-guarded" plane-parallel chambers in electron beams when the front face of the cavity is the effective point of measurement. There is experimental evidence that ion chambers which are not well-guarded (e.g., Markus) have nonunity P(repl) values. Monte Carlo simulations are employed in this study to investigate the replacement correction factors for plane-parallel chambers in electron beams. Using previously established Monte Carlo calculation methods, the values of P(repl) are calculated with high statistical precision for the cavities of a variety of plane-parallel chambers in a water phantom irradiated by various electron beams. The dependences of the values of P(repl) on the beam quality, phantom depth, as well as the guard ring width are studied. In the dose fall-off region for low-energy beams, the P(repl) values are very sensitive to depth. It is found that this is mainly due to the gradient effect, which originates from the fact that the effective point of measurement for many plane-parallel chambers should not be at the front face of the cavity but rather shifted toward the center of the cavity by a fraction of a millimeter. Using the front face of the cavity as the effective point of measurement, the calculated values of P(repl) at d(ref) are not unity for some well-guarded plane-parallel chambers. The calculated P(repl) values for the Roos chamber are close to 1 for all electron beams. The calculation results for the Markus chamber are in good agreement with the measured values. The appropriate selection of the effective point of measurement for plane-parallel chambers in electron beams is an important issue. If the effective point of measurement is correctly accounted for, the P(repl) values would be almost independent of depth. Both the guard ring width and the ratio of the collecting volume diameter to the cavity thickness can influence the values of P(repl) For a diameter to thickness ratio of 5 (e.g., NACP02 chamber), the guard width has to be 6 mm for the chamber to be considered as well-guarded, i.e., have a P(repl) value of 1.00.

Monte Carlo calculations of correction factors for plane‐parallel ionization chambers in clinical electron dosimetry

Recent standard dosimetry protocols recommend that plane-parallel ionization chambers be used in the measurements of depth-dose distributions or the calibration of low-energy electron beams with beam quality R50 <4 g/cm2. In electron dosimetry protocols with the plane-parallel chambers, the wall correction factor, Pwall, in water is assumed to be unity and the replacement correction factor, Prepl, is taken to be unity for well-guarded plane-parallel chambers, at all measurement depths. This study calculated Pwall and Prepl for NACP-02, Markus, and Roos plane-parallel chambers in clinical electron dosimetry using the EGSnrc Monte Carlo code system. The Pwall values for the plane-parallel chambers increased rapidly as a function of depth in water, especially at lower energy. The value around R50 for NACP-02 was about 10% greater than unity at 4 MeV. The effect was smaller for higher electron energies. Similarly, Prepl values with depth increased drastically at the region with the steep dose gradient for lower energy. For Markus Prepl departed more than 10% from unity close to R50 due to the narrow guard ring width. Prepl for NACP-02 and Roos was close to unity in the plateau region of depth-dose curves that includes a reference depth, dref. It was also found that the ratio of the dose to water and the dose to the sensitive volume in the air cavity for the plane-parallel chambers, Dw/[Dair]pp, at d(ref) differs significantly from that assumed by electron dosimetry protocols.

SU-GG-T-207: Monte Carlo Calculations of Correction Factors for Plane-Parallel Ionization Chambers in Clinical Electron Dosimetry

Purpose: To calculate the wall correction factor, Pwall and the replacement correction factor Prepl for NACP-02, Markus, and Roos plane-parallel chambers in clinical electron dosimetry using the EGSnrc Monte Carlo code system. Method and Materials: Pwall was calculated as the ratio of the dose to the sensitive volume of the air cavity in a chamber wall composed entirely of water to that in a real chamber wall. Prepl was obtained with dividing the ratio of the dose to water at the point of measurement (0.1 mm thickness) to the dose of sensitive volume of the air cavity by the stopping-power ratios. Results: Pwall for NACP-02 increased from 1.005 to 1.136 for 4 MeV and from 1.007 to 1.023 for 18 MeV, at a depth between near-surface to R50. Similarly, Pwall increased from 1.004 to 1.079 and from 1.002 to 1.023 for Markus, and from 1.001 to 1.079 and from 1.004 to 1.023 for Roos. Pwall at a reference depth, dref, decreased from 1.019 to 1.008 for NACP-02, from 1.019 to 1.005 for Markus, and from 1.015 to 1.006 for Roos, in a range of 4 MeV to 18 MeV. Also, Prepl for NACP-02 increased from 0.973 to 1.079 for 4 MeV and from 0.996 to 1.017 for 18 MeV, at a depth between near-surface to R50. Similarly, the Prepl values increased from 0.938 to 1.172 and from 0.992 to 1.022 for Markus, and from 0.982 to 1.055 and from 1.000 to 1.010 for Roos. Prepl at dref for NACP-02 and Roos was 0.999±0.3% and 1.000±0.3%, respectively, in a range of 4 MeV to 18 MeV. Prepl for Markus varied from 0.987 to 0.995 because of a narrow guard ring width. Conclusion: This study indicated the need for the change to Pwall and Prepl values used in current dosimetry protocols.

Dependence of Device Structures on Latchup Immunity in a High-Voltage 40-V CMOS Process With Drain-Extended MOSFETs

The dependence of device structures on latchup immunity in a 0.25-mum high-voltage (HV) 40-V CMOS process with drain-extended MOS (DEMOS) transistors has been verified with silicon test chips and investigated with device simulation. Layout parameters such as anode-to-cathode spacing and guard ring width are also investigated to find their impacts on latchup immunity. It was demonstrated that the drain-extended NMOS with a specific isolated device structure can greatly enhance the latchup immunity. The proposed test structures and simulation methodologies can be applied to extract safe and compact design rule for latchup prevention of DEMOS transistors in HV CMOS process

Systematic derivation of latchup design rules for submicron CMOS processes from test structures

A dedicated set of test structures can be used to determine the latchup susceptibility of a process as a function of n +p +-spacing, placement of N well and substrate contacts and guardring width and distance to the injecting junction. A systematic approach is given for the translation of these test structure data into latchup design rules resulting in latchup robust products. The methodology is demonstrated using data from a submicron CMOS process on p −/p ++ epitaxial substrates.

Design model and guidelines for n-well guard ring in epitaxial CMOS

This work reports the development of design model for n-well guard rings in a CMOS process utilizing a low-doped epitaxial layer on a highly doped substrate. The validity of the model has been judged by a wide range of experimental data measured from the fabricated n-well guard ring structures with guard ring width as parameter. From the model developed, guidelines have been drawn to minimize the guard ring width while critically suppressing the amount of electrons escaping from the guard ring. >

Analytical design formulation for minority-carrier well-type guard rings in CMOS circuits

Minority carriers injected from an active emitter into the substrate and partially collected by the bottom well junction in an epitaxial CMOS structure are studied. Two-dimensional numerical simulation has revealed that the minority-carrier collection current along the bottom well junction is contributed primarily by two mechanisms: the first due to minority carriers injected into a layer between the upper collecting plate and the bottom reflecting plate; and the second due to those penetrating the high/low junction and then spreading out in the large, highly-doped bulk as in the nonepitaxial case. Based on this observation, a new analytic model for the minority-carrier escape current has been developed as a measure of well-type guard ring efficiency. This model, including a closed-form expression as function of epitaxial layer thickness, well junction depth and guard ring width, has been confirmed by experimental data as well as by two-dimensional numerical simulation. As predicted by the model, the measured escape current has been found to be dominated by the second mechanism for the case of well junction depth close to epitaxial layer thickness while the first mechanism has been identified to dominate the escape current measured from the structure having sufficient epitaxial layer thicknesses.

Thermal Conductivity Measurement with the Plate Apparatus: Influence of the Guard Ring Width on the Accuracy of Measurement

The temperature field in circular and square plate test specimens is calculated and thereby the error from the heat exchange at the outer edge of the guard ring derived for single and double plate devices contact. The error is shown to be proportional to the reduced temperature difference (difference between the mean specimen and the ambient temperatures divided by the difference between the hot and cold plate tem peratures) and the margin of error, therefore, can be optimally reduced by an appro priate adjustment in the ambient temperature. Experiments on an extruded foam confirm the results of the analytical calculations. Diagrams and tables which are de veloped on the basis of the above derived relationships make possible estimation of margin of error for different measuring arrangements for plate devices of usual sizes.