Systematic derivation of latchup design rules for submicron CMOS processes from test structures

Abstract

A dedicated set of test structures can be used to determine the latchup susceptibility of a process as a function of n +p +-spacing, placement of N well and substrate contacts and guardring width and distance to the injecting junction. A systematic approach is given for the translation of these test structure data into latchup design rules resulting in latchup robust products. The methodology is demonstrated using data from a submicron CMOS process on p −/p ++ epitaxial substrates.