Optimization of Well-Type Guard Rings in Epi Cmos

Abstract

We report first the work of optimizing n-well guard rings in a given epitaxial CMOS process (see Fig. 1) based on our developed models published in [l] and [2]. Properly designing n-well guard ring is of growing importance for suppressing latch-up and charge upset of the internal circuitry; however, the corresponding area cost should be simultaneously taken into account. This design consideration is needed especially for the worst noisy conditions. The developed model 11-21 for the escape current Ic2 labeled in Fig.1 has been presented as function of epitaxial layer thickness, well junction depth, and guard ring width. This model is foumulated analytically 8s Icl = Ieff * exp(- Wg/(i!(Xepi-Xjd)/X)) where Wg is the guard ring width, %pi is the epitaxial layer thickness, Xjd is located at the edge of the depletion region of the bottom reverse-biased well-substrate junction, and Ieff is the current parameter to be fitted. This model can be interpreted properly by the mechanism due to minority carriers injected into a layer between the upper collecting plate and the bottom reflecting plate [l-21. All the test structures have been fabricated by the 1.0 um epi CMOS process. The corresponding doping profiles have been measured, from which we have accurately determined the values of %pi and Xjd. Therefore, the parameter Ieff, which involves complex mechanisms such as high-level injection and three-dimensional distribution nature, can be easily extracted as long as the escape currents have been measured as function of guard ring width Wg and of forward bias Vbe. The corresponding results have been judged to be valid, as demonstrated in Fig. 2 and 3. Moreover, the escape currents can thus be accurately predicted by the model( see Fig. 4 for the comparisons of the measured and predicted escape currents as function of Vbe biases for different guard ring widths ranging from 5 um to 60 um). Therefore, the empirically-constructed model can be properly utilized to optimize the guard ring widths for a critical value of escape current to trigger the latch-up or charge upset of the internal circuitry. The corresponding design window will be reported in detail. Moreover, the associated studies of the measured guard ring collection currents Icl (see Fig.5) and the two-dimensional simulation results (see Fig6 ) will also be reported to highlight the work.