Gate Turn-off Thyristor Research Articles

The First Optimisation of a 16 kV 4H-SiC N-Type IGCT

A challenge in the development of Silicon carbide (SiC) gate turn-off thyristors lie in an uneven transient behaviour, necessitating expensive snubbers. To address these limitations and simplify circuit topology we present an optimized 16 kV n-type SiC integrated gate commutated thyristor (IGCT) design, which utilises a novel highly doped base strip (HDBS). A particular focus is on optimizing the gate commutation of the GCT during switching, and the trade-offs in the HDBS base design were investigated. The findings reveal that compared with conventional GCT design, the HDBS design under high current conditions recorded a 11.8% reduction in turn-off power losses. When simulating the device in a high-voltage scenario, the HDBS IGCT demonstrated a 3.9% reduction in turn-off power losses and an improved turn-on power loss performance. This resulted in a reduction of power losses by 12.1% and 2.3% in high current and high voltage conditions, respectively. In summary, the novel SiC HDBS IGCT design paves the way towards a secure, high current density, and low loss switching SiC thyristor device.

Physical insight into turn‐on transient of silicon carbide gate turn‐off thyristor

AbstractSilicon Carbide (SiC) Gate Turn‐off (GTO) thyristor is regarded as a promising option for pulsed power applications; however, the formation of high di/dt has been constrained by the slow current rise transient phase and the turn‐on current heterogeneity over the chip device. In this paper, a practical integrated multi‐cell simulation is performed to physically characterize the turn‐on transient of SiC GTO thyristor. Through examining electrical coupling between adjacent cells caused by both parasitics of electrode metallization and carrier travelling via SiC, the current distributions are observed, and the carrier transport dynamics are analyzed in detail. Furthermore, physical mechanisms dominating the current heterogeneity among multi‐cells are discovered in depth. It is revealed that the current heterogeneity during the turn‐on transient is primarily resulted from the Gate signal delay caused by the Gate Runner metallization, and the lateral interaction from adjacent semiconductor regions adds to this inhomogeneity; however, this situation can be improved once the electrical distance between each Anode contact and the Anode electrode gets lowered. Design method for turn‐on performance improvement is also proposed accordingly. Besides, based on the analysis conducted on the multi‐cell simulation results, the possible reason of the extremely slow current rise transient phase is speculated and experimentally verified. The improvement in the comprehension of SiC GTO's turn‐on transient, which cannot be obtained from the traditional investigation from the viewpoint of one elementary cell, will provide guiding principles helping in directing future efforts to advance the improvement of device design technology.

Simulation Study of 4H-SiC Low Turn-Off Loss and Snapback-Free Reverse-Conducting Gate Turn-Off Thyristor with N-Float Structure

In this study, a novel integrated 4H-SiC reverse-conducting gate turn-off thyristor (GTO) featuring an N-type floating (NF) structure is proposed. The proposed NF-structured 4H-SiC GTO outperforms conventional reverse-conducting GTOs in forward conduction, effectively eliminating the snapback phenomenon. This is achieved by increasing lateral resistance above the P-injector and modifying the electron current path during early turn-on. NF structures with a doping concentration of 2 × 1014 cm−3 and thicknesses exceeding 4 μm have been indicated to successfully eliminate the snapback phenomenon. Moreover, the anode-shorted structure enhances the GTO’s breakdown voltage and concurrently reduces turn-off losses by 85% at low current densities.

A mathematical model of an electric drive system including GTO thyristors

A mathematical model of an electric drive system including GTO thyristors

Modeling and Analysis of SiC GTO Thyristor’s Dynamic Turn-On Transient

The fast turn-on speed of silicon carbide (SiC) gate-turn-off (GTO) thyristor is preferred for pulse power applications. However, the turn-on delay phenomenon hinders its improvement. In this article, the dynamic turn-on transient process of SiC GTO thyristor is investigated and analyzed extensively by means of both numerical simulation and physical modeling. The physical mechanism behind its turn-on transient process is discussed in detail. A physical model based on the charge-control theory is proposed to identify the dominant factors influencing the dynamic turn-on transient. Then the theoretical analysis is quantitatively made on the parameter design of GTO’s unit cell, and methods to increase the turn-on switch speed are extensively discussed. This study provides not only in-depth physical insights into the device’s turn-on characteristics, but also designs guidelines for the advancement of SiC GTO thyristor.

Comparative Model of Single-phase AC Cycloconverter for 1000Wp Photovoltaic Grid-connected 220VAC-50Hz

Currently, the Electrical Engineering Laboratory (EEL) of Universitas Jenderal Achmad Yani has a 1 kWp photovoltaic (PV) system. However, in order to fulfill the overall load, the hybrid link to the grid must be improved. The PV system and the grid must be synchronized in terms of voltage, frequency, and phase. This article presents comparative simulations of AC-AC converter models of power electronics component variants using MATLAB 2019a. Among other stages is to model the DC-DC Converter in order to enhance the output voltage of the solar panel by identifying the circuit characteristics. The second stage involves simulating the MOSFET-based DC-AC Converter circuit, which is used to convert DC to AC. The use of switching Thyristor, Gate Turn-Off Thyristor (GTO), and Insulated Gate Bipolar Transistor (IGBT) in an AC-AC phase converter to connect to the grid is examined in this range. Non-linear and linear loads are used to represent the load on the AC Cycloconverter range. Based on the results of the modeling and analysis of the PV 1 kWp system, the AC Cycloconverter in the first stage may provide a frequency of 50 Hz with a voltage drop of 235.4 V for the line and 231.9 V for the non-linear, which meets the AC Cycloconverter criterion.

Evaluation of Ultrahigh-Voltage 4H-SiC Gate Turn-OFF Thyristors and Insulated-Gate Bipolar Transistors for High-Power Applications

Technology-based computer-aided design models have been used to predict the static and dynamic performance of ultrahigh-voltage (UHV) 4H-silicon carbide (SiC) P-i-N diodes, insulated-gate bipolar transistors (IGBTs), and gate turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> (GTO) thyristors designed for 20–50 kV blocking voltage capability. The simulated forward voltage drops of 20–50 kV device designs range between 3.1 and 5.6 V for P-i-N diodes, 4.2–10.0 V for IGBTs, and 3.4–7.8 V for GTO thyristors at 20 A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> for room temperature operation. Moreover, with a low switching frequency application (i.e., 150 Hz) in mind, the switching energy losses using a 30 kV SiC GTO thyristor design are approximately E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> _ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GTO</sub> = 268/640 mJ, E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> _ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FWD</sub> = 388/6 mJ diode recovery losses, and <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">E</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> / <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">E</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> _ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SNUB</sub> = 954/22 mJ snubber component losses. The corresponding values for an SiC IGBT design are <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">E</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> / <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">E</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> _ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IGBT</sub> = 983/748 mJ, both operated at 448 K, <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">τ_A</i> = 20 μs, and with 30 A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The simulation output is used in a benchmark evaluation for a 1 GW, 640 kV application case, employing modular multilevel high-power converter legs comprising series-connected UHV SiC devices and state-of-the-art 4.5 kV Si bi-mode insulated-gate transistors. It is concluded that the high-voltage SiC power electronic building blocks present promising alternatives to existing high-voltage Si device counterparts in terms of system compactness and efficiency.

Optimization techniques for p-GTO thyristor design

A new type of semiconductor power device was devised in the early ’90s as an alternative to the classic Gate Turn-Off (GTO) thyristor. Because the low-doped n-base was replaced by a low-doped p-base, it was called the p-GTO. Its main advantage is a higher possible control voltage when the device is switched off, leading to the possibility of a higher blocking anode current (IATO) and a lower turn-off time. The studies and techniques employed with the help of SILVACO-TCAD simulation software Athena and Atlas show that the p-GTO has higher breakdown voltages compared with its classic counterpart and similar on-state voltage (VT) and switching characteristics when replacing the GTO in the same circuit. Specific circuit improvements, like an affordable higher turn-off gate voltage, will drive the p-GTO into even faster switching operation.

A multiple-floating-zone-assisted graded-step-JTE for high-voltage 4H-SiC GTO thyristor

A multiple-floating-zone-assisted graded-step-JTE for high-voltage 4H-SiC GTO thyristor

A Compact Spice Model for SiC Gate Turn-Off Thyristors With Complete Parameter Extraction Procedure

In this article, a compact subcircuit model for silicon carbide (SiC) gate turn-off thyristors (GTOs) is developed in which static (including conduction and blocking) and dynamic characteristics are completely covered for the first time. The proposed model is composed of two improved 2T-3R models in parallel, and the delay between different submodels is represented by capacitance and resistance. The DC voltage source and variable capacitance are added to reflect the conductivity modulation effect in the forward conduction state, and parasitic effects are also considered. A complete extraction procedure is set up to determine all model parameters (including transistor parameters) from calculation and measurement curves. The model is validated by comparing the simulation results of the model with the experimental results of a self-fabricated 4H-SiC GTO, and the results show a high degree of accuracy.

A SiC gate turn-off thyristor with high di/dt for fast switching-on applications

High di/dt 4H-silicon carbide (SiC) gate turn-off thyristors (GTOs) are investigated and developed for fast switching-on application. This work has focused on accelerating the turn-on process to improve the di/dt characteristic, and the n-base dopant concentration is carefully designed to increase the injection efficiency of top P+N junction. With reducing n-base dopant concentration from 2.3 × 1017cm−3 to 6.8 × 1016cm−3, the injection efficiency is increased about 18%, and consequently the current rise-up process and subsequent lateral propagation of the anode current are obviously accelerated. Experimental results show that the di/dt capability is greatly improved and a high di/dt of 126 kA cm−2 μs−1 is obtained. The excellent di/dt performance makes the designed 4H-SiC GTO a promising candidate for fast switching-on application.

Dynamic Performance Enhancement of an Armature Controlled Separately Excited D.C. Motor

In this paper the dynamic performance (speed regulation performance versus reference and load torque changes) of a separately excited D.C. motor is enhanced, the D.C. motor is fed by a D.C. source through a chopper which consists of GTO thyristor and free-wheeling diode. The motor drives a mechanical load characterized by inertia J, friction coefficient B, and load torque TL. The performance enhancement is achieved by using a speed control loop uses a proportional-integral (PI) controller which produces the reference signal for the current control loop and this is a (PI) current controller compares the sensed current with the reference and generates the trigger signal for the GTO thyristor to force the motor current to follow the reference. The simulation of the D.C. drive is performed using MATLAB/Simulink program version 7.10 (R2010a).

Enhancing gate turn-off thyristor blocking characteristics by low temperature defect passivation technology

In the past, gate turn-off (GTO) thyristors were commonly used to either increase the length of the drift region or reduce the doping concentration to increase high-voltage and high-power applications. However, this results in an on-resistance (R on) increase. In this study, we applied a supercritical fluid (SCF) treatment to devices which has the advantage of high permeability and low-temperature processing to passivate SiC-GTO bulk defects. After the proposed defect passivation, the breakdown voltage has been improved by 8% without increasing on-state resistance. In addition, the leakage current has also been suppressed more than 30% in average. This study also uses electrical analysis to understand the characteristics of the devices after SCF treatment, and then discusses the passivation mechanism of materials of the devices from this treatment.

Atomistic Mechanism of 4 H - SiC/SiO2 Interface Carrier-Trapping Effects on Breakdown-Voltage Degradation in Power Devices

The $\mathrm{Si}\mathrm{C}/{\mathrm{Si}\mathrm{O}}_{2}$ interface in the termination area is a crucial component in limiting high-temperature reverse-bias (HTRB) reliability for $\mathrm{Si}\mathrm{C}$-based high-voltage devices. However, the atomic structure and carrier-trapping behavior of the $\mathrm{Si}\mathrm{C}/{\mathrm{Si}\mathrm{O}}_{2}$ interface defects therein and the underlying physical mechanisms of breakdown-voltage (${V}_{\mathrm{BD}}$) variation are still largely unclear. Here, the $\mathrm{Si}\mathrm{C}/{\mathrm{Si}\mathrm{O}}_{2}$ interface defects of 4H-$\mathrm{Si}\mathrm{C}$ gate turn-off (GTO) thyristors before and after HTRB stress are investigated by transient capacitance measurements and density-functional-theory (DFT) calculations. It is found that the bias stress at 4.4 kV enlarges the interface state density at ${E}_{C}\ensuremath{-}0.60$ eV to ${E}_{C}\ensuremath{-}1.33$ eV by electron capturing. As a result, the negative interface charge is generated. As high-resolution transmission electron microscopy reveals the presence of excess carbon near the $\mathrm{Si}\mathrm{C}$ surface, DFT calculations are focused on carbon-related interface defects to clarify the atomic and electronic structures of the $\mathrm{Si}\mathrm{C}/{\mathrm{Si}\mathrm{O}}_{2}$ interface trap and assign them to negatively charged excess split-interstitial carbon at the interface. Furthermore, technical computer-aided-design simulation further proves that the negatively charged $\mathrm{Si}\mathrm{C}/{\mathrm{Si}\mathrm{O}}_{2}$ interface defect is the main cause for the observed ${V}_{\mathrm{BD}}$ degradation after the HTRB test, which leads to a strong electric field crowding effect. These results not only provide deep physical insights underlying ${V}_{\mathrm{BD}}$ degradation in HTRB-stressed high-voltage devices, but are also of significant importance in the optimizations of device structure and oxidation technology for $\mathrm{Si}\mathrm{C}/{\mathrm{Si}\mathrm{O}}_{2}$ interfaces in high-voltage $\mathrm{Si}\mathrm{C}$ devices.

A High-Resolution In Situ Condition Monitoring Circuit for SiC Gate Turn-Off Thyristor in Grid Applications

Silicon carbide (SiC) gate turn-off (GTO) thyristor is attractive for grid applications due to the excellent performances of high blocking voltage and low ON-resistance. However, the short-circuit reliability issue has become one of the limiting factors. An in situ condition monitoring method for the reliability of SiC GTO is presented in this work. It uses the forward I- V characteristics of anode-gate p-n junction as the reliability degradation precursor of SiC GTO. The monitoring circuit shows a current resolution of 64 μA with the current range of -31~1027 mA. It provides full electrical isolation with 2-kV isolation voltage. Finally, a set of short-circuit power cycling tests are conducted with the monitoring circuit, and the results show that the method proposed in this article can effectively detect the change of I- V characteristics of SiC GTO to predict the degradation of device physical health.

EXPERIMENTAL MODEL OF SINGLE-PHASE DC–DC BOOST CONVERTER FOR 1000 WP PHOTOVOLTAIC APPLICATION

The photovoltaic system is used and utilized as electricity demand in many developed countries, including Indonesia. Nowadays, the photovoltaic system is an alternative source of inexpensive, reasonably priced electricity and easily applied in public facilities until laboratory usage. In Electrical Engineering Laboratory (EEL), Faculty of Engineering (FoE), Universitas Jenderal Achmad Yani is 1 kWp peak photovoltaic application available. The PV system is planned to be connected to the grid and produces 220VAC / 50Hz characteristics to meet the existing load capacity. The PV systems modeled include Pulse Width Modulation (PWM) controlled DC/DC Boost Converter, and DC/AC converter circuit. This study's experimental architecture is proposed to meet the electrical load following the characteristics of the photovoltaic device. The three types of electronic switching control, namely Metal Oxide Semiconductor Field Effect Transistor (MOSFET), Insulated Gate Bipolar Transistor (IGBT) and Gate Turn-off Thyristor (GTO), are used to achieve the highest performance. Based on the 1 kWp photovoltaic system's simulation results from the three types of electronic power switching, a minimum output voltage range of 210-230 VDC is produced. DC/AC Converter testing has been carried out and can be tested on a grid-connected 220VAC/50Hz single phase with the highest output using MOSFET equal to 96.7%.

Switching overvoltages protection of power electronics converters with gate turn-off thyristors

Using the developed models in the “Simulink” visual programming environment of the “Matlab” application package using the “SimPowerSystem” and “Simscape Electrical” libraries, a comparative analysis of methods and techniques for limiting switching overvoltages in power converters, which are controlled by unlocking two-operation thyristors, was performed. The choice of a specific means of limitation is individual for each converter and depends on many factors - the power of the converter, the current-voltage characteristics of thyristors, the parameters of the power supply, and so on. Studies have shown that the most effective protection against voltage pulses with short duration and significant amplitude is the use of “Transient Voltage Suppressors” limiting diodes, the action of which is based on the use of avalanche breakdown during the time of thyristor unlocking.

Identification of Gate Turn-off Thyristor Switching Patterns Using Acoustic Emission Sensors.

Modern seagoing ships are often equipped with converters which utilize semiconductor power electronics devices like thyristors or power transistors. Most of them are used in driving applications such as powerful main propulsion plants, auxiliary podded drives and thrusters. When it comes to main propulsion drives the power gets seriously high, thus the need for use of medium voltage power electronics devices arises. As it turns out, power electronic parts are the most susceptible to faults or failures in the whole electric drive system. These devices require efficient cooling, so manufacturers design housings in a way that best dissipates heat from the inside of the chips to the metal housing. This results in susceptibility to damage due to the heterogeneity of combined materials and the difference in temperature expansion of elements inside the power device. Currently used methods of prediction of damage and wear of semiconductor elements are limited to measurements of electrical quantities generated by devices during operation and not quite effective in case of early-stage damage to semiconductor layers. The article presents an introduction and preliminary tests of a method utilizing an acoustic emission sensor which can be used in detecting early stage damages of the gate turn-off thyristor. Theoretical considerations and chosen experimental results of initial measurements of acoustic emission signals of the medium voltage gate turn-off thyristor are presented.

Surface Recombination and Excess Current of Anode-Gate Mesa Sidewall in 4H-SiC Gate Turn-Off Thyristor

The forward and reverse I-V characteristics of Anode-Gate diodes passivated with pyrogenic and dry oxide in4H-SiC gate turn-off thyristor (GTO) were investigated by device size dependent measurement. The bulk and surface current component were manifested and separated, where the surface recombination velocity was accurately evaluated as 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> -10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> cm/s. Pyrogenic oxide was found more effective than dry oxide to suppress surface traps induced excess carrier recombination and carrier generation at etched p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> n mesa sidewall. Moreover, temperature dependent measurement revealed that excess current of Anode-Gate diodes is primarily attributed to carrier recombination and generation from surface traps. Surface traps dominates the reverse leakage below 125 °C, while electrically active bulk defects contributes to the reverse leakage simultaneously at elevated temperature. Finally, the influence of passivation on the 4H-SiC GTOs forward characteristics was demonstrated. Higher gate trigger current needed to switch from blocking to conduction state for the 4H-SiC GTOs with dry oxide passivated Anode-Gate mesa sidewall.

Investigation on 4H-SiC gate turn-off thyristor with direct carrier extraction access to drift region for power conversion applications

4H-SiC gate turn-off (GTO) thyristor offers extraordinary advantages over its counterparts in handling ultra-high voltage electric power conversion applications because of its relatively low forward voltage drop at high conduction current density. Besides, though the SiC thyristors never suffer from long carrier liftime induced large switching loss like Si thyristors, the peak temperature rise rather than dynamic avalanche breakdown is blamed for the safe operation area (SOA) failure, making further reduction of power loss in SiC GTOs even more important. In this paper, a 20 kV SiC GTO with direct carrier extraction access to its drift region (DA-GTO) is investigated to explore the benefit this structure could bring for SiC thyristors, namely achieving smaller switching loss and/or potential larger SOA with slight sacrifice in forward voltage drop at high current. The structure is formed by interleaved P+ ion implantation into part of the thin N-injector layer based on conventional 20 kV SiC GTO. The SiC DA-GTO operates in BJT mode at low current, and in GTO mode with low forward voltage drop at high current. During turn-off process, it offers a direct current path to quickly sweep out the excess carriers in the P-drift region, thus speeds up the turn-off process and decreases the turn-off loss. Simulation results show that its turn-off loss reduces by 37.4%, contributing to 12.6% reduction in total power loss, compared with SiC GTO. Therefore, SiC DA-GTO is a very promising choice for next-generation power conversion systems.