Growth Of Si Layers Research Articles

Si-Passivated Ge Gate Stacks with Low Interface State and Oxide Trap Densities Using Thulium Silicate

Ultra-thin epitaxially grown Si layers have been used for Ge surface passivation in CMOS devices utilizing standard silicon SiO2/HfO2 gate stack. In this work, we propose a high-k TmSiO interfacial layer, which has shown excellent performance on Si, instead of the chemical SiO2. We successfully transfer a TmSiO/Tm2O3/HfO2 gate stack from silicon to Si-passivated Ge devices, yielding interface state density of 3·1011 eV-1cm-2, which is comparable to GeOx passivation. Moreover, Si-capped Ge gates with TmSiO interfacial layer achieve significant improvement in oxide trap density compared to GeOx passivation, exhibiting a potential for superior reliability. We further investigate the robustness of Si layer growth process and show that small (±3˚C) variations of growth temperature can be detrimental to the interface state density of the gate stacks.

Several Specifics of Silicon Atom Condensation on the Surface of a Tungsten Single Crystal

Field emission microscopy was used to study Si condensation on a W surface by varying substrate temperature T and number n of monoatomic layers of the precipitated condensate. A low-temperature Si monolayer with a pure W structure formed at lower temperatures of T ~ 600 K, while another structure of a high-temperature surface silicide monolayer formed at T ≥ 1000 K. The orienting effect additionally differed between the low-temperature monolayer and surface silicide during further growth of Si layers. Pure Si crystallites formed starting from the third monolayer (n ≥ 3) in the case of condensation on the low-temperature monolayer and starting from n ≥ 300 monolayers in the case of condensation on surface silicide. Estimates were obtained for the activation energy Qdif of Si diffusion into the W lattice and the desorption energy Qdes of Si atoms from the W surface.

Features of the Initial Stage of the Heteroepitaxy of Silicon Layers on Germanium When Grown from Silicon Hydrides

Data on the dependence of the growth rate of Si layers deposited onto Ge(111) by the hydride method on their thickness at the initial heteroepitaxy stage are reported. The effect of a Ge substrate within ten grown silicon single layers on the Si-film growth rate is demonstrated. Based on the data obtained, the kinetic coefficients responsible for the rate of the main physicochemical processes related to the interaction of hydride molecular beams with the growth surface are calculated. An analysis of the capture probability and rates of pyrolysis of the adsorbed Si(Ge) hydride molecules on the pure Ge(Si) surfaces reveals the dependence of their behavior on the growing-layer thickness. Comparison of the results obtained during Si-layer growth on Ge shows that the pure germanium surface has higher adsorption and catalytic abilities with respect to silane molecules than the pure Si surface. The unstrained pure Si surface has higher adsorption and catalytic characteristics with respect to Ge-hydride molecules.

Fundamental Characteristics of Cyanide‐Related Multielement Molecular Ion‐Implanted Epitaxial Si Wafers for High‐Performance CMOS Image Sensors

Fundamental characteristics such as metal‐gettering capability and defect morphology of a cyanide‐related multielement molecular (CH4N) ion‐implanted epitaxial silicon (Si) wafer are investigated. It is found that the CH4N ion‐implanted epitaxial Si wafer has a higher gettering capability for transition metallic impurities than a hydrocarbon molecular (C3H5) ion‐implanted epitaxial Si wafer. This higher metal‐gettering capability of the CH4N ion‐implanted epitaxial Si wafer may be due to the formation of stacking faults as well as carbon (C) agglomeration defects in the CH4N ion‐implanted region during the epitaxial Si layer growth process. The formation of stacking faults may be a specific phenomenon in the case of the CH4N ion implantation. In addition, the CH4N ion‐implanted region can trap high concentrations of hydrogen (H) and nitrogen (N) atoms during the epitaxial Si growth. This fact suggests that the distribution of N atoms is strongly associated with the defect morphology and C distribution in the CH4N ion‐implanted region. The CH4N ion‐implanted epitaxial Si wafer with these characteristics has the potential to improve the performance of complementary metal‐oxide‐semiconductor (CMOS) image sensors.

Особенности начальной стадии гетероэпитаксии слоев кремния на германии при их выращивании из гидридов кремния

AbstractData on the dependence of the growth rate of Si layers deposited onto Ge(111) by the hydride method on their thickness at the initial heteroepitaxy stage are reported. The effect of a Ge substrate within ten grown silicon single layers on the Si-film growth rate is demonstrated. Based on the data obtained, the kinetic coefficients responsible for the rate of the main physicochemical processes related to the interaction of hydride molecular beams with the growth surface are calculated. An analysis of the capture probability and rates of pyrolysis of the adsorbed Si(Ge) hydride molecules on the pure Ge(Si) surfaces reveals the dependence of their behavior on the growing-layer thickness. Comparison of the results obtained during Si-layer growth on Ge shows that the pure germanium surface has higher adsorption and catalytic abilities with respect to silane molecules than the pure Si surface. The unstrained pure Si surface has higher adsorption and catalytic characteristics with respect to Ge-hydride molecules.

Abrupt SiGe-to-Si interface: influence of chemical vapor deposition processes and characterization by different metrology techniques

Future electronic (gate-all-around transistors) and photonic devices (electro-absorption modulator and laser stack) will require SiGe/Si multilayer stacks with abrupt interfaces. Chemical vapor deposition (CVD) is a proven method to epitaxially grow such multilayer structures. However, the abruptness of the compositional change is limited by Ge segregation occurring during Si layer growth on a (Si)Ge surface. Here, we study the compositional abruptness at the interface between Si0.70Ge0.30 and Si layers epitaxially grown in a CVD reactor. The ultra-thin interface layer between SiGe and Si is characterized by transmission electron microscopy, secondary ion mass spectrometry and spectroscopic ellipsometry (SE). Our results show that a Si layer grown using a chlorinated chemistry produces the most abrupt interface. For Si deposition processes with non-chlorinated chemistry, lower growth temperature and a higher order hydride precursor result in a reduced transition thickness. Furthermore, we show that the interface thickness measured by the different metrology techniques are in good agreement, suggesting that SE can be used to evaluate the ultra-thin interface at the Si0.70Ge0.30-to-Si interface, resulting in considerably shorter development time in a production environment.

Growth mechanisms for Si epitaxy on O atomic layers: Impact of O-content and surface structure

The epitaxial growth of Si layers on Si substrates in the presence of O atoms is generally considered a challenge, as O atoms degrade the epitaxial quality by generating defects. Here, we investigate the growth mechanisms for Si epitaxy on O atomic layers (ALs) with different O-contents and structures. O ALs are deposited by ozone (O3) or oxygen (O2) exposure on H-terminated Si at 50°C and 300°C respectively. Epitaxial Si is deposited by chemical vapor deposition using silane (SiH4) at 500°C. After O3 exposure, the O atoms are uniformly distributed in Si-Si dimer/back bonds. This O layer still allows epitaxial seeding of Si. The epitaxial quality is enhanced by lowering the surface distortions due to O atoms and by decreasing the arrival rate of SiH4 reactants, allowing more time for surface diffusion. After O2 exposure, the O atoms are present in the form of SiOx clusters. Regions of hydrogen-terminated Si remain present between the SiOx clusters. The epitaxial seeding of Si in these structures is realized on H-Si regions, and an epitaxial layer grows by a lateral overgrowth mechanism. A breakdown in the epitaxial ordering occurs at a critical Si thickness, presumably by accumulation of surface roughness.

Kinetics modeling and growth of Si layers by Liquid Phase Epitaxy Driven by Solvent Evaporation (LPESE)

Crystalline Si thin films on low-cost substrates are expected to be an alternative to bulk Si for PV applications. Liquid Phase Epitaxy (LPE) is one of the most suitable techniques for the growth of high quality Si layers since LPE is performed under almost equilibrium conditions. We investigated a growth technology which allows growing Si epitaxial thin films in steady temperature conditions through the control of solvent evaporation from a metallic solution saturated with silicon: Liquid Phase Epitaxy by Solvent Evaporation (LPESE). An analytical model aiming to predict solvent evaporation and Si crystallization rate is described and discussed for three solvents (Sn, In and Cu). Growth experiments are implemented in order to check the validity of the model. Experimental set up and growth procedure are presented. Si thin films were grown from Sn–Si and In–Si solution at temperatures between 900 and 1200°C under high vacuum. The predicted solvent evaporation rate and Si growth rate are in agreement with the experimental measurements.

Application of crystalline silicon surface oxidation to silicon heterojunction solar cells

We study the effect of ultra-thin oxide (SiOx) layers inserted at the interfaces of silicon heterojunction (SHJ) solar cells on their open-circuit voltage (VOC). The SiOx layers can be easily formed by dipping c-Si into oxidant such as hydrogen peroxide (H2O2) and nitric acid (HNO3). We confirm the prevention of the undesirable epitaxial growth of Si layers during the deposition of a-Si films by the insertion of the ultra-thin SiOx layers. The formation of the SiOx layers by H2O2 leads to better effective minority carrier lifetime (τeff) and VOC than the case of using HNO3. c-Si with the ultra-thin SiOx layers formed by H2O2 dipping, prior to deposition of a-Si passivation layers, can have high implied VOC of up to ∼0.714 V.

A New Method to Induce Tensile Stress in Silicon on Insulator Substrate: From Material Analysis to Device Demonstration

Channel deformation has been proven as an effective way to increase performance of Field Effect Transistor [1]. In advanced technology nodes, in order to obtain good electrostatic control of the device, fully depleted channel become mandatory and devices such as FinFET or Fully Depleted Silicon On Insulator (FD-SOI) are developed. In these devices, channel deformation can be obtained by using strained SOI (sSOI) substrate fabricated by specialized manufactured companies. The traditional sSOI fabricaton required (i) a relaxed buffer of SixGe(1-x) in order to form a strain Si layer by epitaxy on the top of it and (ii) the use of a bond and split process suitable to strained layer [2]. Here, we propose an alternative methodology [3]. The new sSOI substrates are fabricated and analyzed. Si stress higher than 1.4GPa is obtained. The so-fabricated substrates are used to process Complementary Metal Oxide FD-SOI (sSOI CMOS FD-SOI) devices at 14nm node design rules. For nFET devices, improvement in mobility is demonstrated with respect to devices built on standard SOI substrates. To elaborate sSOI substrates, starting materials are classical SOI wafers with Si layer thicknesses between 7 and 11nm. The process flow is shown in the figure. Epitaxial growth of 20nm thick Si0.73Ge0.27 is performed above SOI. Si ions are then implanted. Implantation conditions are chosen in order to totally amorphize the Si on insulator layer and to partially amorphize the bottom of the Si0.73Ge0.27 layer: indeed a crystalline layer is needed at the surface of the Si0.73Ge0.27 layer for further crystallization. The remaining crystal seed is shown in the TEM picture. Next; the sample is submitted to a crystallization anneal. During the implantation and annealing step the crystal seed is partially relaxed. Thereby, a relaxed Si0.73Ge0.27 lattice parameter is imposed to the Si on insulator during crystallization. The strain analysis by TEM shown in the figure demonstrates the partial relaxation of the Si0.73Ge0.27 and the tensile strain inside the Si. Some structural defects can be identified in the Si0.73Ge0.27 layer after anneal. These defects could play a role the Si0.73Ge0.27 relaxation. The relaxation mechanism will be in the presentation. Finally the Si0.73Ge0.27 layer is selectively removed from the wafer surface. As measured by substrate bow variations, the stress in the Si film is in the range of 1.4 - 1.5GPa. This value is roughly the one expected for an epitaxial Si layer growth on a relaxed Si0.8Ge0.2. CMOS FD-SOI devices have been processed at 14nm node design rules on the so-fabricated sSOI substrates as well as on standard SOI substrates for comparison. C doped Si is used as raised source drain for the n FET. The pFET features are a Si0.75Ge0.25 channel and a Si-Ge alloy raised source drain. Compared to devices built on standard SOI substrates, sSOI devices show threshold voltage shift coherent with tensile stress. Channel mobilities were extracted in short and long channel devices. As expected with tensile stress, sSOI devices showed increased mobility in nFET devices and decreased one in pFET devices. [1] SW Bedell et al, MRS Bulletin, Vol 39, p 131, 2014 [2] M Bruel, US Patent, US 00 5 374 564A, 1994 [3] A. Halimaoui, et al., Patent EP 2 787 118 A1, 2014 Figure : Illustration of the process flow used for sSOI fabrication. TEM characterizations at various process steps. Figure 1

Surfactant role of Ag atoms in the growth of Si layers on Si(111)√3×√3-Ag substrates

The growth of Si layers on Si(111)√3×√3-Ag substrates was studied for coverages of up to a few mono-layers. Atomically flat islands were observed to nucleate in the growth at 570 K. The top surfaces of the islands were covered in Ag atoms and exhibited a √3×√3 reconstruction with the same surface state dispersions as Si(111)√3×√3-Ag substrates. These results indicate that the Ag atoms on the substrate always hop up to the top of the Si layers.

Vacuum hydride epitaxy of silicon: kinetics of monosilane pyrolysis on the growth surface

Analytical expressions relating the rate of silicon atom incorporation into a growing crystal to the typical frequency of silane molecule pyrolysis on the silicon surface in the growth temperature range are derived. Based on currently available experimental data, the range of typical decomposition frequencies of hydride molecule radicals adsorbed at the silicon wafer surface in the temperature range of 450–700°C is determined for the most widely used physicochemical models. It is shown that the most probable molecular decomposition model can be chosen based on the experimental study of the temperature dependence of the decomposition rate of adsorbed hydride molecules. A change in the silane molecule pyrolysis rate or the hydrogen desorption rate from the surface in principle makes it possible to increase the Si layer growth rate without additional substrate heating under conditions of low-temperature epitaxy (450–550°C), but no larger than by a factor of 2–3 in the former case and up to 100 times in the latter case. The analysis performed shows that physicochemical pyrolysis models in which hydrogen is trapped by the surface, mostly at the stage of decomposition of silane radicals adsorbed by the surface, are more realistic.

Analysis of ambient gas influence on silicon layers crystallized by means of LPE

Epitaxial growth of thin layers from the liquid phase can occur with the use of solutions saturated under different ambient gases. Most often this process takes place in a vacuum or gaseous atmosphere of hydrogen or argon. As the experimental data show, the morphology of crystallized layers is determined by the ambient type in which the process occurs.The cohesion energy responsible for epitaxial lateral deposition processes on the substrate surface depends on the surface free energy which is a measure of attraction of the solution atoms by substrate atoms. In the case of crystallization of an epitaxial lateral layer of Si on a substrate partially masked with dielectric, the chemical potentials of atoms in the neighboring phases (determining the interface evolution) are not without influence on the relaxation velocity of the saturated liquid phase, and on the horizontal and vertical growth rate.The aim of the investigation was to analyze experimentally the influence of the ambient gases used during the LPE growth on the cohesion of the Sn–Si solution with substrates applied for the lateral epitaxial growth of Si layers. This work presents comparative temperature analysis of the wetting angle of such surfaces as Si, SiO2 and SiNx by the Sn–Si solution.

Formation of extended defects in SiGe/Si heterostructures with SiGeC intermediate layers

AbstractThe generation of misfit dislocations (MDs) and stacking faults (SFs) was studied by TEM and preferential chemical etching in multilayer Si(001)/SiGe/SiGeC(10 nm)/SiGe/Si heterostructures grown by CVD at 650 °C. Prior to growth of Si layer, the other part of heterostructure was annealed at 950 °C in the growth chamber to get relaxed buffer layers and strained Si layer free of extended defects. We used SiGe alloys with Ge content of 24 at.% and C content of 0.5 at.%. Carbon in the strained SiGe matrix was found to promote high rates of strain relaxation through the nucleation of perfect dislocation loops close to the interface with Si substrate. For Si layer thickness >10 nm, threading dislocations split in these layers under tensile strain to form SFs. (© 2007 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Liquid Phase Epitaxial Growth of Si Layers on Si Thin Substrates from Si Pure Melts under Near-Equilibrium Conditions

The growth of Si epitaxial layers on Si substrates from Si pure melts was attempted under near-equilibrium conditions by dipping-type liquid phase epitaxial (LPE) growth, in order to eliminate the doping effect from metal solutions on the purity of the Si epitaxial layers. Si epitaxial layers can be grown on Si substrates from a Si pure melt only when the temperature of the Si growth melt is kept 1–2°C above the melting point of Si (1414°C) and the growth melt is cooled just after the substrate is dipped in the growth melt. The Si substrate, Si epitaxial layers, and Si polycrystals can be clearly distinguished in the electron back-scattering diffraction pattern (EBSP) image of their cross sections. The growth rate of Si LPE layers during cooling clearly increases as the amount of overheating of the growth melt decreases from 2 to 1°C and the cooling rate increases from 0.4 to 1.0 mm/min.

Formation and properties of selectively grown Ge/Si quantum dots

The selective epitaxial growth of Si layers and Ge quantum dots in windows patterned in oxidized Si(001) was investigated. The selectively deposited Si layers were found to develop towards truncated pyramids limited by {113} facets until the (001) top face disappears. By this way, the Ge dot formation on the (001) surface can then be controlled by adjusting the height of the truncated Si(001) pyramids grown prior to Ge deposition. By monitoring the facet formation during the growth of the Si layers, we showed that it is possible to form single or several Ge dots per window. We have then investigated the formation of Ge dots in stacked selectively grown layers. The Ge dots exhibit a vertical ordering along the growth direction. The optical and electrical properties of Ge dots grown both by selective growth and by self-assembly were investigated. The photoluminescence measurements showed a blue shift of the PL signal from selective Ge dots and the absence of PL from wetting layers as a result of dot size reduction and restricted surface. The forward current–voltage characteristics of Schottky contacts with Ge dots just below the interface exhibit some idealities which can be related to the presence of these dots and indicate that the inhomogeneities are stronger for samples with multilayers of Ge dots.

Formation of heavily P-doped Si epitaxial film on Si(1 0 0) by multiple atomic-layer doping technique

Phosphorus (P) incorporation process during Si epitaxial growth by SiH 4 reaction in ultraclean low-pressure chemical vapor deposition (CVD) and the electrical characteristics of the heavily P-doped epitaxial Si film on Si(1 0 0) have been investigated. Si layer growth on the P layer formed on Si(1 0 0) at 500 °C at SiH 4 partial pressure of 6 Pa is observed when the surface P amount becomes below 7×10 14 cm −2. It is also found that about 1.1×10 14 cm −2 P atoms segregate onto the Si surface and the other desorbs. On the other hand, by lowering the Si growth temperature to 450 °C and increase in the SiH 4 partial pressure to 220 Pa, P incorporation occurs and about 1.5×10 14 cm −2 P atoms are buried at the initial position without segregation. By using the multiple atomic-layer doping technique, very low-resistive heavily P-doped epitaxial Si film on Si(1 0 0) can be formed with effective suppression of the electrically inactive P formation.

Si TWINNING SUPERLATTICE: GROWTH OF NEW SINGLE CRYSTAL Si

Si twinning superlattices are grown on [Formula: see text] by the repeated growth of Si layers with a unit thickness and postgrowth annealing. In order to determine the growth conditions of the Si twinning superlattice, it is essential to measure the crystallographic orientations in the surface regions during growth. Reflection high-energy electron diffraction (RHEED) is very sensitive to the surface orientation. Using the technique to estimate the fraction of the twinned layers in the grown layers by RHEED, we investigate the growth process and thermal stability of the twinned epitaxial layers. The growth of the twinning superlattices is monitored by the oscillation of the twinned layer fraction as a function of the thickness.

Boron incorporation with and without atomic hydrogen during the growth of doped layers on Si(100)

Solid source molecular beam epitaxy Si growths were done with and without atomic hydrogen (AH) to investigate the impact of AH on B segregation and activation. A series of 3 or 50 nm thick B-doped Si layers separated by 200 nm of undoped Si were grown at 0.1 nm/s on Si(100) substrates. In separate experiments, 10−4 Pa of AH was applied after (at 500, 600, and 710 °C) or during (at 710 °C) the 3 nm B-doped layer to determine if AH affected segregation. AH was applied before the 50 nm B-doped layer to observe if AH increased B activation between 600 and 800 °C. It was found that application of AH after the growth of the 3 nm B-doped layer had no effect on B segregation through 600 °C and increased B segregation at 710 °C, as measured by secondary ion mass spectrometry (SIMS). Application of AH during B-doped Si layer growth had no effect on B segregation. Application of 10−3 Pa of AH for 100 s prior to growth of the 50 nm B-doped layer improved surface order, as measured by low energy electron diffraction, and, at T⩾700 °C, increased B activation, as measured by spreading resistance profilometry (SRP). The differences between the SIMS and SRP data are postulated to be due to two forms of B: one electrically active and the other electrically inactive. The electrically inactive form is modeled by two paired B atoms on adjacent substitutional sites.

Er/O and Er/F doping during molecular beam epitaxial growth of Si layers for efficient 1.54 μm light emission

Er, together with oxygen or fluorine as co-dopants, has been incorporated into Si during molecular beam epitaxial growth using co-evaporation of Si and Er containing compounds. The Er doping concentration using both Er2O3 and ErF3 can reach a level of ∼5×1019 cm−3 without precipitation, which is at least one order of magnitude higher than a previously reported solid solubility limit for Er in Si. Growth, structural, and luminescence characterization of these Er/O and Er/F doped Si samples are reported. In particular, 1.54 μm electroluminescence has been observed from Er/O doped Si layers at room temperature through hot electron impact excitation.