Graded Channel Gate Stack Research Articles

Study of DC and Analog/RF Performances Analysis of Short Channel Surrounded Gate Junctionless Graded Channel Gate Stack MOSFET

Study of DC and Analog/RF Performances Analysis of Short Channel Surrounded Gate Junctionless Graded Channel Gate Stack MOSFET

Performance Assessment of Graded Channel Gate-Stack based Double Gate MOSFET for Bio-sensing Applications

Performance Assessment of Graded Channel Gate-Stack based Double Gate MOSFET for Bio-sensing Applications

Analog/RF Performance of Graded Channel Gate Stack Triple Material Double Gate Strained-Si MOSFET with Fixed Charges

The performances of analog/RF parameters of a graded channel gate stack triple material double gate (GCGS-TMDG) strained-Silicon (s-Si) MOSFET with fixed charges are analyzed by using Sentaurus TCAD simulator. For the GCGS-TMDG s-Si MOSFET, analog/RF parameters, such as early voltage, transconductance generation factor (TGF), voltage gain, unity gain frequency (ft), gain frequency product (GFP), transconductance frequency product (TFP), and gain transconductance frequency product (GTFP), are estimated for various device parameters (i.e., strain in the silicon channel, fixed charge density with damaged length, and thicknesses of different high-k dielectric materials). The simulated data shows that the proposed GCGS-TMDG s-Si MOSFET obtains lower values of drain current and output conductance compared to the graded channel gate stack double gate (GCGS-DG) s-Si MOSFET. Besides, the GCGS-TMDG s-Si MOSFET provides superior performances of early voltage, ft, GFP, TFP, and GTFP in comparison with the GCGS-DG s-Si MOSFET in strong inversion region, and vice-versa in weak inversion region.

A Two-Dimensional (2D) Analytical Modeling and Improved Short Channel Performance of Graded-Channel Gate-Stack (GCGS) Dual-Material Double-Gate (DMDG) MOSFET

A Double-gate (DG) metal-oxide-semiconductor field effect transistor (MOSFET) is emerging device architecture in sub-nanometer regime. The performance of DG MOSFET can be ameliorated by gate and channel engineering. The concept of graded-channel gate-stack (GCGS) and dual-material (DM) are incorporated in DG MOSFET. A two-dimensional (2D) analytical surface potential model for GCGS DMDG MOSFET is developed based on the solution of Poisson’s equations with appropriate boundary conditions. It has been found that analytically modeled data is in good degree of agreement with numerically simulated data. The combination of both DM and GC concept introduces a step variation in potential profile at the junction of both materials in channel region and ameliorates the short channel effects (SCEs). A suppressed subthreshold swing (SS) and drain induced barrier lowering (DIBL) has been observed in the device due to an elevated average velocity of carrier and reduced drain field effect by the use of DM and GC with GS. Further, analog/RF characteristics such as transconductance generation factor (TGF), cut-off frequency (fT) and transconductance frequency product (TFP) have been examined with different GS high-k dielectrics. The numerically simulated data has been extracted using 2D ATLAS device simulator.

Surface Potential Modeling of Graded-Channel Gate-Stack (GCGS) High-K Dielectric Dual-Material Double-Gate (DMDG) MOSFET and Analog/RF Performance Study

In each complementary metal-oxide-semiconductor (CMOS) technology generation, design of new device architectures at nanoscale regime becomes quite challenging task due to increased short channel effects (SCEs) and leakage current. A double-gate (DG) MOSFET is an alternative structure. To enhance the performance of DG MOSFET, gate stack (GS) and dual-material gate (DMG) with graded-channel (GC) concepts are amalgamated. Analytical surface potential modeling of GCGS DMDG MOSFET has been done by solving the two-dimensional (2D) Poisson’s equation with suitable boundary conditions. The surface potential profile of GCGS DMDG MOSFET shows a step variation at the interface of two materials. The electrical parameters drain induced barrier lowering (DIBL), sub-threshold swing (SS) and on-current to off-current $\left (\frac {I_{on}}{I_{off}}\right )$ ratio reveals that, DMDG shows a better performance over single-material (SM) DG MOSFET with all (Si3N4, HfO2 and Ta2O5) GS high-k dielectric configurations. An enhanced performance in GCGS DMDG is due to the fact of increased average carrier velocity, reduced drain field effect and leakage current. Further, analog/RF performance parameters such as transconductance (gm), transconductance generation factor (TGF), cut-off frequency (fT), transconductance generation frequency product (TGFP), gain frequency product (GFP) and gain transconductance frequency product (GTFP) are extracted and compared for both SMDG and DMDG MOSFET with HfO2 GS configuration. The efficacy of analytically modeled results is compared with numerically simulated results obtained from 2D ATLAS device simulator.

Influence of Channel Length and High-K Oxide Thickness on Subthreshold DC Performance of Graded Channel and Gate Stack DG-MOSFETs

Comparative assessment of graded channel gate stack (GCGS) DG MOSFET structure is done by using two-dimensional (2D) Sentrausu TCAD simulator for different high K oxide thickness. This novel device includes gate stack (GS) engineering (high K) and nonuniformly channel engineering (GC) to suppress the short channel effects and improve the device performance. This novel device can be a better alternative for the future high speed switching and low power circuit applications. It has the advantage of improved breakdown voltage, reduced leakage current, low output conductance and reduced bipolar parasitic effects. The given device must be properly investigated with respect to the variation of different high K oxide thickness on different parameters such as drain induced barrier lowering (DIBL), subthreshold slope (SS), [Formula: see text]/[Formula: see text], [Formula: see text] roll off before fabrication to have better reliability. The 2D Sentrausu TCAD simulator using drift-diffusion model was used to simulate the developed structure and good agreement is obtained with respect to already published result in the sub-threshold regime. The result indicates that there is a need to be optimize the DC parameters for specific circuit applications.

Influence of channel length and high-K oxide thickness on subthreshold analog/RF performance of graded channel and gate stack DG-MOSFETs

In this paper, the graded channel gate stack (GCGS) DG MOSFET structure is studied in view of increasing device performance and immunity to short channel effects. The device has the advantage of improved gate oxide reliability, suppressed parasitic bipolar effect, lower DIBL and higher cut-off frequency. Therefore, the device must be investigated with respect to the variation of different structure dependent parameters before fabrication to have better reliability and constancy. In this work we have studied the device with respect to variation in high K oxide thickness (toxh) and channel length (Lg) to have better understanding on variation of different analog/RF performance parameters. The results validate that variations in toxh of the device significantly alters device performance parameters and must be pre accounted for realizing reliable analog/RF system on chip circuits.

An analytical two dimensional subthreshold behavior model to study the nanoscale GCGS DG Si MOSFET including interfacial trap effects

In order to pursue the miniaturization process as predicted by Moor’s law and go beyond actual reached lengths, more condensed efforts should be focused not only on looking for higher mobility materials but also on improving existing topologies of nanocircuit digital devices, which are the corner stone of currently used information storage supports. Therefore, the aim of this paper is to provide a quantitative analysis about the efficiency of our proposed structure Graded Channel Gate Stack Double Gate on Si MOSFET (GCGS DG Si MOSFET) in remedying the short channel and hot carrier degradation effects. The analysis is carried out by using an analytical 2-D subthreshold behavior model consolidated with numerical simulations (SILVACO), where the proposed structure shows an improvement and immunity against the hot carriers in terms of threshold voltage and swing factor. Moreover, the developed analytical models including the device immunity effect are compared with those of the conventional DG MOSFET, where a significant enhanced performance is predicted for the case of our proposed design. Consequently, it can be reasonably claimed that the (GCGS) DG Si MOSFET structure can alleviate the short channel and hot carrier degradation effects and further improves the device reliability for the nanoelectronic digital applications.

Subthreshold behavior optimization of nanoscale Graded Channel Gate Stack Double Gate (GCGSDG) MOSFET using multi-objective genetic algorithms

In this paper, a multi-objective genetic algorithms-based approach is proposed to study and optimize the subthreshold behavior of Graded Channel Gate Stack Double Gate (GCGSDG) MOSFET for nanoscale CMOS digital applications. The subthreshold parameters such as threshold voltage, drain induced barrier lowering (DIBL), subthreshold swing and OFF-current have been ascertained and mathematical models have been proposed. The proposed mathematical models are used to formulate the objectives functions, which are the pre-requisite of genetic algorithm. The overall objective function is formulated by means of weighted sum approach. Thus, the proposed approach is used to search for optimal subthreshold parameters to obtain better electrical performances of the devices for digital application.

A two-dimensional analytical analysis of subthreshold behavior to study the scaling capability of nanoscale graded channel gate stack DG MOSFETs

In this paper, a new nanoscale graded channel gate stack (GCGS) double-gate (DG) MOSFET structure and its 2-D analytical model have been proposed, investigated and expected to suppress the short-channel-effects (SCEs) and improve the subthreshold performances for nanoelectronics applications. The model predicts a shift, increasing potential barrier, in the surface potential profile along the channel, which ensures a reduced threshold voltage roll-off and DIBL effects. In the proposed structure, the subthreshold current and subthreshold swing characteristics are greatly improved in comparison with the conventional DG MOSFETs. The developed approaches are verified and validated by the good agreement found with the numerical simulation. (GCGS) DG MOSFET can alleviate the critical problem and further improve the immunity of SCEs of CMOS-based devices in the nanoscale regime.