Abstract
In this paper, a multi-objective genetic algorithms-based approach is proposed to study and optimize the subthreshold behavior of Graded Channel Gate Stack Double Gate (GCGSDG) MOSFET for nanoscale CMOS digital applications. The subthreshold parameters such as threshold voltage, drain induced barrier lowering (DIBL), subthreshold swing and OFF-current have been ascertained and mathematical models have been proposed. The proposed mathematical models are used to formulate the objectives functions, which are the pre-requisite of genetic algorithm. The overall objective function is formulated by means of weighted sum approach. Thus, the proposed approach is used to search for optimal subthreshold parameters to obtain better electrical performances of the devices for digital application.
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