Glass Interposer Research Articles

Via-First Process to Enable Copper Metallization of Glass Interposers With High-Aspect-Ratio, Fine-Pitch Through-Package-Vias

A via-first process for metallizing copper on glass substrates is presented using a thin, patternable polymer film, electroless copper deposition, and semiadditive processing. A procedure for partially precuring the polymer was developed in order to achieve a tented via structure after dry-film lamination and curing. The flexibility of the process is demonstrated by the use of plasma etching, CO2, and UV laser ablation as patterning technologies. Metallization by electroless copper deposition and semiadditive processing is shown to be conformal, continuous, and without defects on the surface and in the vias as demonstrated by cross-sectional analysis. Glass of $100~\mu \text{m}$ thickness with vias of 10– $20~\mu \text{m}$ diameter and $40~\mu \text{m}$ pitch was metallized to demonstrate the dimensional capability of the process. Thermomechanical reliability was validated by copper peel testing after highly accelerated stress testing and daisy-chain resistance measurements taken throughout thermal cycle testing.

A Novel Sealing Redistribution Layer Approach for Through-Glass via Fabrication

A sealing redistribution layer (RDL) approach for the interposer fabrication is developed to simplify the conventional bottom-up process flow. By using this approach, bottom-up plating can achieve the integration of Cu-filler plating and its bottom RDL simultaneously. In this paper, through-glass via in glass interposer or 3-D integration is fabricated using the proposed approach. The electrical measurement and reliability tests indicate that the proposed approach can be an attractive candidate for interposer fabrication with great performance.

Fast and Cost-Effective Superconformal Filling of High Aspect Ratio through Glass Vias Using MTT Additive

Cu superconformal filling of through glass vias (TGV) of aspect ratios (AR) 6 and 10 for glass interposer applications is achieved at greatly reduced times of about 1 h and 4 h, respectively, compared to about 3 h and 12 h in the past. The DC electroplating is carried out in the presence of the additive thiazolyl blue tetrazolium bromide (MTT) in acidic (pH 2 to 4) copper methane sulfonate (CuMSA)/Cl− formulations. The applied plating conditions enable the ‘butterfly’ mechanism that nucleates hemispherical or X-shaped Cu plugs in the TGV's centers while keeping the thickness on external surfaces low. Plugs are formed in AR 6 TGV's in as little as 12 min, after which the plating can be viewed as the filling of double-sided blind vias. Issues with imperfections trapped in the plugs have been addressed by decreasing the current around the time of plug formation, then increasing it for the rest of the process. In order to fill AR 10 holes much longer times at lower current density are needed. Larger diameter AR 4 TGV's have been also successfully filled with Cu. Lab scale quantities of MTT are 8 to 14 times less expensive than the competing additives NTBC and TNBT, respectively.

Precision Cutting of Glass by Laser-assisted Machining

Precision machining of glass has been receiving attention in various applications because of the use of glass interposers in layered semiconductors or glass substrates for microfluidic chips. These applications require complicated and three-dimensional machining for further product functionality. Etching is conventionally used for precision machining of glass. However, applying etching for three-dimensional machining is difficult, and thus, a method which is applicable to three-dimensional machining of glass is needed. Cutting is a method applicable to three-dimensional machining. However, precision cutting of glass is difficult because glass is a hard and brittle material. In this research, we applied laser-assisted machining for cutting of glass. We first conducted laser-assisted milling for plane surface cutting. We then proposed laser-assisted drilling for glass drilling to perform the three-dimensional cutting of glass by laser-assisted machining. Through the experimental analyses, we demonstrated the feasibility of the precision and three-dimensional cutting of glass.

Measurement and Analysis of Glass Interposer Power Distribution Network Resonance Effects on a High-Speed Through Glass Via Channel

In this paper, we measured and analyzed glass interposer power distribution network (PDN) resonance effects on a high-speed through glass via (TGV) channel for the first time. To verify the glass interposer PDN resonance effects on the TGV channel, glass interposer test vehicles were fabricated. With these test vehicles, glass interposer PDN impedance, channel loss, far-end crosstalk, and eye diagram are measured. Based on these measurements, glass interposer PDN resonance effects on the signal integrity of the high-speed TGV channel are analyzed. Due to low loss of the glass substrate, sharp high PDN impedance peaks are generated at the resonance frequencies. High PDN impedance peaks at the PDN resonance frequencies, which affect return current of the TGV channel, increase channel loss, crosstalks, and PDN noise coupling in the frequency domain and degrade eye diagram in the time domain. To suppress these glass interposer PDN resonance effects, a ground shielded-TGV scheme is proposed. The proposed ground shielded-TGV scheme includes two ground TGVs $200\;{{\mu \text{m}}}$ away from the signal TGV considering the design rules and includes package ground underneath the glass interposer. Effectiveness of the suggested grounding scheme on the resonance effects suppression is verified with three-dimensional electromagnetic simulation. The proposed shielded-TGV design successfully suppressed the glass interposer PDN resonance effects that results in the suppression of insertion loss, shielding of the crosstalk, and improvement of the eye diagram of the high-speed TGV channel.

High- $k$ Thin-Film Capacitors With Conducting Oxide Electrodes on Glass Substrates for Power-Supply Applications

High- $k$ barium strontium titanate (BST) thin films were deposited onto glass substrates to demonstrate integrated capacitors for power supply in high-speed digital packages. Ferroelectric BST films were sputter deposited onto solution-derived lanthanum nickel oxide (LNO) electrodes. Zirconium oxide was studied for the first time as a barrier between glass and LNO electrodes to prevent electrode (LNO) interdiffusion into the glass substrate. The LNO and BST films were annealed in an oxygen-rich atmosphere at 650 °C. A capacitance density of 20–30 nF/mm2 was obtained at an operating voltage of 3 V. Leakage currents of 1–10 nA/nF were measured up to 3 V. These properties demonstrate the potential for low-cost high- $k$ thin-film decoupling capacitors in 2-D, 2.5-D, and 3-D glass interposers. A process to integrate and test such capacitors on glass substrates using sequential dielectric and electrode patterning is also demonstrated.

Design and Demonstration of Fine-Pitch and High-Speed Redistribution Layers for Panel-Based Glass Interposers at 40-μm Bump Pitch

This article analyzes redistribution layer (RDL) technologies needed for 2.5-dimensional (2.5-D) die integration on thin glass interposers and developed using low-cost processes. The design, fabrication, and characterization of a four-metal layer RDL buildup required for wide input/output (I/O) routing at 40-μm bump pitch and a two-metal layer RDL buildup fabricated directly on glass for high-speed, off-package signaling are described. Such RDL technologies are targeted at 2.5-D glass interposer packages to achieve up to 1 Tb/s die-to-die bandwidth and off-interposer data rates > 400 Gb/s, driven by consumer demand of online services for mobile devices. Advanced packaging architectures including 2.5-D and 3-D interposers require fine-line lithography beyond the capabilities of current organic package substrates. High electrical loss and high cost are characteristic of silicon interposers fabricated using back-end-of-line (BEOL) processes that can achieve RDL wiring densities required for 2.5-D die integration. Organic interposers with high wiring densities have also been demonstrated using a single-sided, thin-film process. This article goes beyond silicon and organic interposers in demonstrating fine-pitch RDL on glass interposers fabricated by low-cost, double-side, and panel-scalable processes. The high modulus and smooth surface of glass help to achieve lithographic pitch close to that of silicon. Furthermore, the low permittivity and low loss tangent of glass reduce dielectric losses, thus improving high-speed signal propagation. A semiadditive process flow and projection excimer laser ablation were used to fabricate four-metal layer (2 + 0 + 2) fine-pitch RDL and two-metal layer RDL directly on glass. A minimum of 3 μm lithography and 20 μm microvia pitch was achieved. High-frequency characterization of these RDL structures demonstrated single-ended insertion losses of −0.097 dB/mm at f = 1 GHz and differential insertion losses of −0.05 dB/mm at f = 14 GHz.

Design, Modeling, Fabrication and Characterization of 2–5-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math> </inline-formula> Redistribution Layer Traces by Advanced Semiadditive Processes on Low-Cost Panel-Based Glass Interposers

This paper presents the latest advances in extending semiadditive process (SAP) methods to 2–5 $\mu \text{m}$ lines and spaces, achieved using dry film photoresists on thin glass substrates, toward meeting the routing requirements for 20- $\mu \text{m}$ bump pitch interposers. High-density chip-to-chip interconnections on 2.5-D interposers are a key enabler to meet the high logic to memory bandwidth needs of next-generation electronic systems. Such 2.5-D interposers require ultrafine redistribution layer (RDL) traces with line widths and spacing below $5~\mu \text{m}$ . This paper reports on the extension of panel scale and lower cost SAPs to achieve less than $5~\mu \text{m}$ lines and spaces, based on the ultrasmooth surface and improved dimensional stability of thin glass panels. A modified low-cost SAP method with newly developed differential seed layer etching was employed to fabricate the fine line and space patterns and coplanar waveguide (CPW) transmission on thin glass panels. Fine lines down to 2- $\mu \text{m}$ lines and spaces and CPW lines with signal lengths up to 5 mm and ground-to-signal gaps down to $5.5~\mu \text{m}$ at 15- $\mu \text{m}$ signal widths were successfully fabricated on ultra-thin glass panels. For comparison, the same processes were also applied to a silicon wafer. The signal insertion losses of CPW lines on the glass were 0.024 dB/mm better at 15 GHz than those on the silicon, as confirmed by simulations as well as VNA measurements. The measured insertion loss of 5-mm long CPW lines on glass interposer was 0.7 dB at 10 GHz and matched well to the simulated values.

Glass interposer for short reach optical connectivity.

We propose a glass interposer containing femtosecond laser-scribed waveguides to interconnect silicon photonic chips. The glass interposer has an insertion loss of about 1.5 dB/cm, and simplifies alignment of silicon photonic chips. Our experiment shows that the insertion loss for the grating coupler/inscribed glass interface was only 0.5 dB higher than the estimated coupling loss of grating coupler to SMF. The 3 dB coupling degradation occurs after 5 µm of in-plane displacement between the laser-inscribed waveguide and the grating coupler.

Multi-scale thermal modeling of glass interposer for mobile electronics application

Purpose – The functionality of personal mobile electronics continues to increase, in turn driving the demand for higher logic-to-memory bandwidth. However, the number of inputs/outputs supported by the current packaging technology is limited by the smallest achievable electrical line spacing, and the associated noise performance. Also, a growing trend in mobile systems is for the memory chips to be stacked to address the growing demand for memory bandwidth, which in turn gives rise to heat removal challenges. The glass interposer substrate is a promising packaging technology to address these emerging demands, because of its many advantages over the traditional organic substrate technology. However, glass has a fundamental limitation, namely low thermal conductivity (∼1 W/m K). The purpose of this paper is to quantify the thermal performance of glass interposer-based electronic packages by solving a multi-scale heat transfer problem for an interposer structure. Also, this paper studies the possible improvement in thermal performance by integrating a fluidic heat spreader or vapor chamber within the interposer. Design/methodology/approach – This paper illustrates the multi-scale modeling approach applied for different components of the interposer, including Through Package Vias (TPVs) and copper traces. For geometrically intricate and repeating structures, such as interconnects and TPVs, the unit cell effective thermal conductivity approach was used. For non-repeating patterns, such as copper traces in redistribution layer, CAD drawing-based thermal resistance network analysis was used. At the end, the thermal performance of vapor chamber integrated within a glass interposer was estimated by using an enhanced effective thermal conductivity, calculated from the published thermal resistance data, in conjunction with the analytical expression for thermal resistance for a given geometry of the vapor chamber. Findings – The limitations arising from the low thermal conductivity of glass can be addressed by using copper structures and vapor chamber technology. Originality/value – A few reports can be found on thermal performance of glass interposers. However thermal characteristics of glass interposer with advanced cooling technology have not been reported.

Electrical Modeling and Analysis of Tapered Through-Package via in Glass Interposers

This paper proposes a wideband scalable circuit model for tapered through-package vias (TPVs) in glass interposers. By slicing TPVs horizontally into infinitesimally thin pieces and integrating along TPVs, an analytical solution was derived for the parasitic resistance ( $R$ ), while semianalytical expressions were derived for the parasitic inductance ( $L$ ), capacitance ( $C$ ), and conductance ( $G$ ) in the proposed model. Then, this model was verified against a 3-D electromagnetic solver in terms of S-parameters for various TPV dimensions, with the differences of $S_{21}$ magnitude and $S_{21}$ phases being less than 0.01 dB and 1°, respectively. In addition, two dual-via chains of different lengths were designed, fabricated, and measured to benchmark the proposed model up to 20 GHz. The excellent consistency between them further proves the validity of the proposed model. Finally, the effect of the TPV taper was comprehensively studied on the RLCG parameters. It was found that the TPV taper was beneficial to reduce the parasitic capacitance and conductance by as much as 40%. Despite these benefits, tapered TPVs are not preferred, because the parasitic resistance and inductance are the dominant factors for TPVs in glass, and the TPV taper increases the parasitic resistance drastically and also increases the parasitic inductance by as much as 80%.

Design and Demonstration of Power Delivery Networks With Effective Resonance Suppression in Double-Sided 3-D Glass Interposer Packages

Ultrathin 3-D glass interposers with through-package vias at the same pitch as through-silicon vias (TSVs) have been proposed as a simpler and cheaper alternative to the direct 3-D stacking of logic and memory devices. Such 3-D interposers provide wide-I/O channels for high signal bandwidth (BW) between the logic device on one side of the interposer and memory stack on the other side, without the use of complex TSVs in the logic die. However, this configuration introduces power delivery design challenges due to resonance from: 1) the low-loss property of the glass substrate and 2) the parasitic inductance due to additional length from lateral power delivery path. This paper presents for the first time, the design and demonstration of power delivery networks (PDNs) in 30- $\mu \text{m}$ thin, 3-D double-sided glass interposers, by suppressing the noise from mode resonances. The self-impedance of the 3-D glass interposer PDN was simulated using electromagnetic solvers, including printed-wiring-board and chip-level models. The 3-D PDN was compared with that of the 2-D glass packages having fully populated ball grid array connections. The resonance mechanism for each configuration was studied in detail, and the corresponding PDN loop inductances were evaluated. High impedance peaks in addition to the 2-D PDN were observed at high frequencies (near 7.3 GHz) in the 3-D interposer structure due to the increased inductances from lateral power delivery. This paper proposes and evaluates three important resonance suppression techniques based on: 1) 3-D interposer die configuration; 2) the selection and placement of decoupling capacitors; and 3) 3-D interposer package power and ground stack-up. Two-metal and four-metal layer test vehicles were fabricated on 30- and 100- $\mu \text{m}$ thick panel-based glass substrates, respectively, to validate the modeling and analysis of the proposed approach. The PDN test structures were characterized up to 20 GHz for plane resonances and network impedances, with good model-to-hardware correlation. The results in this paper suggest that the ultrathin 3-D interposer PDN structure can be effectively designed to meet the target impedance guidelines for high-BW applications, providing a compelling alternative to 3-D-IC stacking with the TSVs.

Reliability Evaluation for Integrated Glass Interposer

Reliability Evaluation for Integrated Glass Interposer

Wafer-level packaging for ultra-thin glasses using hermetic room temperature welding technology

The aim of the study was to develop a hermetic package using ultra-thin glass wafers. A novel glass welding technology, with a minimal heat load, was used to construct the encapsulations. Industry requirements of the miniaturization of the electronic components, for example in medical implants and consumer electronics and opto-electronics, challenge the conventional manufacturing technologies and package materials [1]. Low-cost glass interposers and packages have been research by GeorgiaTech at their PRC industry program. Glass packaging can offer even ten times affordable option than using silicon [2]. During the last few years, the advancements in the glass manufacturing technologies have enabled a cost effective production of the ultra-thin glass wafers and panels. Laborious glass grinding process from thick material to ultra-thin is no longer necessary since the fusion forming process can be used. Ultra-thin glass makes it possible to reduce the package size and weight [3]. Typically, glasses thickness of 300 μm or less are considered as ultra-thin material. However, even as thin as 25 μm glass is commercially available [4]. Several methods are used for glass joining including: anodic, fusion, and adhesive bonding [5]. During the recent years increasing number of laser based techniques are applied to glass packaging. Numerous studies have concentrated on frit bonding [6, 7]. Elementary study of the direct laser joining without any additive layers has been demonstrated by Miyamoto et al. [8]. Glass welding method has been further investigated in several researches [9, 10]. The package is constructed of three ultra-thin glass wafers: base and lid, thicknesses of 200 μm and spacer, thickness of 100 μm. Commercially available 6” borosilicate, D263T, wafers are used which were welded together by using novel laser welding technology. Welding is implemented on material interface without using any additive materials or coating layers. Glass surfaces are left untouched and optical quality is retained. Welding was performed on a wafer level and the single packages were cut after the final welding. Hermeticity test was performed to ensure the welding quality. Radioisotope leak test with krypton 85 was performed at Oneida Research Services. The results showed an excellent hermeticity: leak rate less than 6,0×10–12 atmcm3/s Kr-85 was achieved. Limits set in the MIL-standard are easily reached. The study proves that novel glass welding technology can be applied to wafer-level packaging with ultra-thin glasses. Technique eliminates the need of additive materials, and due to the minimal heat load bending and warping of the material can be avoided. Also, glass offers effortless visual inspection through the entire lifetime of the device.

Laser Drilling and Conducting Film Formation of Vias in Silicon

Smaller vias are required to connect interlayers in semiconductor devices, glass interposers, and printed circuit boards. However, plating metals on the inner walls of these fine holes is becoming difficult. We demonstrate that laser illumination of stacked materials results in laser drilling and spontaneous coating of the inner surface. This process drilled through the upper materials of the stack and then evaporated the lower material, which re-deposited on the inner surface of the upper materials. Laser illumination of samples composed of stacked borosilicate glass, silicon, and copper formed vias with diameters of ∼15 μm in the silicon wafer (thickness of 100 μm) and spontaneously deposited the copper film on the inner surface. We observed the inner surfaces of the drilled holes in the silicon wafer with a field-emission scanning electron microscope equipped with an energy-dispersive x-ray spectroscope accessory. The conductivity of the vias was ∼100 Ω. We expect that, by changing the lower material, various materials could be deposited on the upper material, making this technique useful in many applications.

Design and Demonstration of 40 micron Bump Pitch Multi-layer RDL on Panel-based Glass Interposers

This paper describes the design, fabrication, and characterization of a two-metal layer RDL structure at 40 um pitch on thin glass interposers. Such an RDL structure is targeted at 2.5D glass interposer packages to achieve up to 1 TB/s die-to-die bandwidth and off-interposer data rates greater than 400 Gb/s, driven by consumer demand of online services for mobile devices. Advanced packaging architectures including 2.5D and 3D interposers require fine line lithography beyond the capabilities of current organic package substrates. Although silicon interposers fabricated using back-end-of-line processes can achieve these RDL wiring densities, they suffer from high electrical loss and high cost. Organic interposers with high wiring densities have also been demonstrated recently using a single sided thin film process. This paper goes beyond silicon and organic interposers in demonstrating fine pitch RDL on glass interposers fabricated by low cost, double sided, and panel-scalable processes. The high modulus and smooth surface of glass helps to achieve lithographic pitch close to that of silicon. Furthermore, the low loss tangent of glass helps in reducing dielectric losses, thus improving high-speed signal propagation. A semi-additive process flow and projection excimer laser ablation was used to fabricate two-metal layer RDL structures and bare glass RDL layers. A minimum of 3 um lithography and 20 um mico-via pitch was achieved. High-frequency characterization of these RDL structures demonstrated single-ended insertion losses of −0.097 dB/mm at f = 1 GHz and differential insertion losses of −0.05 dB/mm at f = 14 GHz.

Temporary Bonding and Debonding Technologies to Enable Innovative Fan-Out Embedded Interposer for High-Density Applications

As requirements increase for mobile devices to be lighter and thinner and to operate at high speed and high bandwidth, innovations in wafer-level packaging have evolved to 3-D structures, such as package-on-package (PoP), fan-out integration, and through-silicon-via (TSV) interposer architectures. However, wafer-level packaging is still considered to be costly and slow in throughput due to wafer size limitations. In this study, temporary bonding and debonding processes using mechanical or laser release technologies were applied in the fabrication process of an integrated embedded glass interposer as a foundation for 3-D integrated circuit (IC) packaging on panel-level packaging. Glass interposers having dimensions of 10 mm × 10 mm and a thickness of 120 μm were fabricated. The interposers had through-glass vias (TGVs) 25 μm in diameter and 3000 I/O pads of copper under-bump metallization (UBM) and were designed as a nearly full-array type. The interposers were supported by a temporary bonding material on silicon or glass wafers and embedded by built-up dielectric material on which fan-out redistribution circuit layers were deposited. For forming the pattern of the redistribution layer, a UV laser was used to form 75-μm-diameter blind vias, and conductive interconnections were made by a semi-additive process (SAP) using photolithography and electrolytic copper. The process of building up layers from the glass interposer to form an embedded fan-out interposer can eliminate a joining process required by traditional 2.5-D IC integration. Finally, the embedded fan-out carrier is separated from the glass or silicon wafer through a laser debonding process. An experiment to study the correlation of bonding material and release material with built-up lamination in backside processes will be discussed in this paper to address full process integration on panel-size substrates. The combination of temporary bonding technology with mechanical or laser release technologies will pave the way for realizing cost-effective 3-D IC packaging on panel-level substrates.

Advanced lithography and electroplating approach to form high-aspect ratio copper pillars

Advanced packaging technologies continue to enable the semiconductor industry to meet the needs for ever thinner, smaller and faster components required in mobile devices and other high performance applications. In the early days of advanced packaging, C4 solder bumps were the alternative to wire bonding. Although lead-free solder remains one of the preferred methods for assembly, tall copper structures (copper pillars) are becoming the standard interconnect solution for many applications. A process of lithography and subsequent electroplating are the mainstream process for today's copper pillar formation on wafer level for high-end flip chip devices. The latest trends in advanced packaging require another technology development when it comes to copper pillars. Modern integration schemes such as 2.5D interposer as well as 3D stacking have pushed the limits of standard lithography and copper electroplating capabilities. Specifically, the need for fine-pitch high aspect ratio copper pillars represents a challenge. In addition, the trend towards rectangular panel-based packaging as seen with glass interposers or panel fan-out (P-FO) devices demands a challenging scale-up of lithography and electroplating equipment and processing capabilities. This work specifically focuses on the formation of high-aspect ratio copper pillars in excess of 100μm by means of stepper-based lithography followed by electroplating. A unique test vehicle has been created to evaluate the process latitude for lithography for different resist materials as well as the specific electroplating challenges associated with these tall and narrow structures. The paper investigates the influence of key parameters such as CD uniformity, pattern density variations and resist profile on the critically important pillar height uniformity across the wafer or panel. In addition, the resist profile behavior at the substrate interface is being examined as it influences undercut behavior during wet etch of the plating seed layer. A number of wet and dry-film resist materials and appropriate lithography processes (spin coat or laminate, expose, develop) followed by copper plating based on varying chemistries and process parameters are being explored. The paper also summarizes the current requirements for the above mentioned lithography and plating processes as seen in the industry today.

A metal oxide adhesion layer prepared with water based coating solution for wet Cu metallization of glass interposer

Inorganic interposers made of glass are attractive for advanced high frequency applications and ultra- fine line patterning technology. Because glass combines a couple of benefits like large form factor, good coefficient of thermal expansion (CTE) matching to silicon, smooth surface and a low dielectric constant and loss tangent. Recently much progress has been made with respect to glass electrical and physical properties. This allows for handling of thin glass sheets down to 100 μm in a typical PCB panel format. Also advances have been made in the area of laser drilling allowing aspect ratio up to 1:10 for 25 μm diameter of through glass via (TGV). Another major challenge is the cost competitive and reliable metallization of smooth glass, a critical prerequisite for the use of glass substrates in the electronic packaging market. Plated copper does not adhere directly to glass. Sputtering technology typically also requires a 50 nm thick adhesion promoting metal layer (like Ti) before copper can be seeded. This metal layer could not be etched together with the copper and needs to be removed between traces by etching in an additional step. A volatile flammable solvent based metal oxide precursor coating solution has been used to make an adhesive metal oxide layer by a modified sol-gel process. To prevent potential safety issue for mass production water based metal oxide precursor coating solution so called VitroCoat GI W has been developed. The VitroCoat GI W solution can be dip-coated on flat glass surface and TGVs followed by sintering to form an ultrathin metal oxide adhesion layer (about 10nm). The thin adhesive layer enables electroless and electrolytic copper plating directly onto glass substrates without changing any of the glass properties or impacting high frequency performance. The thin metal oxide adhesive layer is non-conductive and can be easily removed from the area between circuit traces. This paper will focus on the coating uniformity and capability of VitroCoat GI W on flat glass surface and TGVs and the adhesion of wet chemical metallization on glass interposer. This adhesion layer can be used for copper fine line patterning on glass and radio frequency (RF) device fabrication.

Impact of Copper Through-Package Vias on Thermal Performance of Glass Interposers

In this paper, the thermal performance of glass interposer substrate with copper through-package vias (TPVs) is investigated both experimentally and numerically. Copper via arrays with different via pitches and diameters were fabricated in 114.3 mm $\times \,\, 114.3$ mm $\times \,\, 100\mu \text{m}$ glass panels using low-cost laser drilling, electroless plating, and electroplating for copper deposition. The thermal performance of such a structure was quantified by measuring an effective thermal conductivity which combines the effect of copper and glass. The effective thermal conductivity of fabricated samples was determined with infrared microscopy and compared with finite-element analysis on unit TPV cell. Using the effective thermal conductivity, further numerical analyses were performed on a 2.5-D interposer, which has two chips mounted side by side with a total heat generation of 3 W. Interconnects and TPV layers in the interposer were modeled as homogeneous layers with an effective thermal conductivity. Using the developed model, the effect of copper TPVs on the thermal performance of silicon and glass interposers was compared. To further characterize the thermal performance of the 2.5-D glass interposer structure, the effects of pitch of interconnects and TPVs and the TPV diameter are presented.