Electrical Modeling and Analysis of Tapered Through-Package via in Glass Interposers

Abstract

This paper proposes a wideband scalable circuit model for tapered through-package vias (TPVs) in glass interposers. By slicing TPVs horizontally into infinitesimally thin pieces and integrating along TPVs, an analytical solution was derived for the parasitic resistance ( $R$ ), while semianalytical expressions were derived for the parasitic inductance ( $L$ ), capacitance ( $C$ ), and conductance ( $G$ ) in the proposed model. Then, this model was verified against a 3-D electromagnetic solver in terms of S-parameters for various TPV dimensions, with the differences of $S_{21}$ magnitude and $S_{21}$ phases being less than 0.01 dB and 1°, respectively. In addition, two dual-via chains of different lengths were designed, fabricated, and measured to benchmark the proposed model up to 20 GHz. The excellent consistency between them further proves the validity of the proposed model. Finally, the effect of the TPV taper was comprehensively studied on the RLCG parameters. It was found that the TPV taper was beneficial to reduce the parasitic capacitance and conductance by as much as 40%. Despite these benefits, tapered TPVs are not preferred, because the parasitic resistance and inductance are the dominant factors for TPVs in glass, and the TPV taper increases the parasitic resistance drastically and also increases the parasitic inductance by as much as 80%.