Impurity Gettering Research Articles

Impurity gettering effect of atomic layer deposited aluminium oxide films on silicon wafers

We present experimental evidence for the impurity gettering effect of atomic layer deposited aluminium oxide (Al2O3) films on silicon wafers, during typical surface passivation activation at 425 °C. Iron was used as a model impurity in silicon to study the gettering effects. Dissolved iron concentrations were determined by carrier lifetime measurements, allowing the iron loss kinetics in silicon wafers with Al2O3 coatings to be monitored during annealing. The redistribution of iron to the surface layers and the sub-surface regions was examined by secondary ion mass spectrometry depth profiling. The results show that the atomic layer deposited Al2O3 films generate a strong gettering effect, removing 50% of the iron after 30 min at 425 °C for a 160-μm thick silicon wafer. The iron reduction process is largely diffusion-limited in the initial stages. The gettering effect is caused by the accumulation of iron at the Al2O3/Si interface.

Leaching behaviors of impurities in metallurgical-grade silicon with hafnium addition

Hf was employed as an impurity getter to enhance the removal of impurities from metallurgical-grade Si (MG-Si) via the solidification of Si or a Si-33wt% Al solvent. The leaching behaviors of the impurities (B, Fe, Al, Ca, P, Zr, Ti, V, Mn, Hf, and Ni) within MG-Si, in the presence of 5wt% Hf, were investigated using various leaching approaches. Compared with aqua regia and HF, HCl+HF was determined to be the optimal lixiviant for the elimination of impurities from Hf-containing MG-Si. The use of a combination of HCl+HF and aqua regia reduced the quantity of impurities from 6126ppmw to 94ppmw. Eh-pH diagrams were calculated to discuss the leaching of HfSi2 in aqua regia and HF solutions. The presence of Hf in the MG-Si enhanced the removal of impurities, especially P, which cannot be efficiently removed via solidification refining and hydrometallurgical treatments. Hf-containing Si-Al solvent refining is considered the most efficient approach for the elimination of impurities (except Al). The removal fractions of B and P were 94.2% and 86.2%, respectively, achieved via the solidification of the Si-33wt% Al solvent. Moreover, 99.94% and 99.9996% of the Hf, used as an impurity getter, could be eliminated through the solidification of the Si and Si-33wt% Al solvent, respectively, decreasing from 50,000ppmw, to 28ppmw and 0.2ppmw, respectively.

Passivation Effects on Low-Temperature Gettering in Multicrystalline Silicon

Annealing at ≤ 500 °C changes minority carrier lifetime in as-grown multicrystalline silicon substantially. Part of the change arises from internal gettering of impurities, but surface passivation for lifetime measurement results in additional effects. We report experiments that aim to clarify the role of passivation. Long-term annealing (up to 60 h) is performed on silicon nitride passivated multicrystalline silicon, and lifetime and interstitial iron concentrations are monitored at each processing stage. Lifetime in all samples is improved under certain conditions, with improvements always achieved at 400 °C. Increases are pronounced in low-lifetime bottom samples, with improvement by a factor of 2.7 at 400 °C or 3.8 at 500 °C. Important differences are found compared with our previous study with iodine–ethanol passivation. First, as-received lifetime is higher with silicon nitride not due to a substantial difference in surface recombination. Second, while interstitial iron concentrations often initially increase with iodine–ethanol, they tend to reduce with silicon nitride. Third, lifetime in high-lifetime samples reduces substantially with iodine–ethanol but increases with silicon nitride. Secondary ion mass spectrometry reveals high iron concentrations in annealed silicon nitride. Results are discussed in terms of gettering of impurities to, and bulk passivation arising from, silicon nitride films.

Impurity Gettering used by Hakoniwa method in Si crystals

Impurity Gettering used by Hakoniwa method in Si crystals

XPS와 SIMS를 이용한 PSG/SiO2/Al-1%Si 적층 박막내의 Na 게터링 분석

In order to investigate the Na gettering, PSG/<TEX>$SiO_2$</TEX>/Al-1%Si multilevel thin films were fabricated. DC magnetron sputter techniques and APCVD (atmosphere pressure chemical vapor deposition) were utilized for the deposition of Al-1%Si thin films and PSG/<TEX>$SiO_2$</TEX> passivations, respectively. Heat treatment was carried out at <TEX>$300^{\circ}C$</TEX> for 5 h in air. SIMS (secondary ion mass spectrometry) depth profiling and XPS (X-ray Photoelectron Spectroscopy) analysis were used to determine the distribution and binding energies of Na, Al, Si, O, P and other elements throughout the PSG/<TEX>$SiO_2$</TEX>/Al-1%Si multilevel thin films. Na peaks were mainly observed at the the PSG/<TEX>$SiO_2$</TEX> interface and at the <TEX>$SiO_2$</TEX>/Al-1%Si interfaces. Na impurity gettering in PSG/<TEX>$SiO_2$</TEX>/Al-1%Si multilevel thin films is considered to be caused by a segregation type of gettering. The chemical state of Si and O elements in PSG passivation appears to be <TEX>$SiO_2$</TEX>.

Purification of metallurgical-grade silicon using zirconium as an impurity getter

Abstract Zr was employed as an impurity getter to enhance removal of impurities from MG-Si because of its strong affinity for a wide range of impurities. Different lixiviants, HCl + HF, HF and aqua regia, were employed to investigate the leaching behavior of MG-Si at 348 K for 2.5 h with and without Zr addition. Typical precipitates at Si grain boundaries before and after acid leaching were observed and analyzed via scanning electron microscopy (SEM) with energy dispersive X-ray spectroscopy (EDS). The leaching results show that the order of efficiency of the lixiviants, from highest to lowest, is HCl + HF > HF > aqua regia. HCl + HF is the optimal lixiviant for purification of MG-Si with and without Zr addition. The presence of Zr in MG-Si can significantly enhance the efficient extraction of impurities, especially P and Al, which cannot be removed efficiently using conventional hydrometallurgical technologies. The total fraction of impurities removed (Fe, Al, Ca, B, P, Zr, Ti, V, Mn, Cu and Ni) increased from 94.2 to 97.5% after HCl + HF leaching. In addition, 99.9% of the impurity getter Zr was removed, with its concentration decreasing from 50,000 ppmw to 49 ppmw after HCl + HF leaching. The residual amount of Zr in the refined Si can be further removed by directional-solidification purification because of its extremely small segregation coefficient.

(Invited) Application of DFT Calculation for the Development of High Quality Si and Ge Substrates: From Ultra Large Diameter Crystal Pulling to Metal Gettering

During the last decade, considerable progress has been made in understanding the properties and behavior of the vacancy V and self-interstitial I in silicon (Si) and germanium (Ge) crystals. This is to a large extent due to the maturing of density functional theory (DFT) calculation techniques and the increase of computing power enabling to calculate not only the formation and migration energies of V and I, but also the interaction with impurities and with crystal surfaces. Furthermore, the impact of internal and external stress on formation and migration enthalpies of both intrinsic point defects has been clarified recently. In this paper an overview will be given of recent results obtained by the author’s group calculating the interaction of V and I with the melt-solid interface, and the impacts of stress and doping on V and I properties. The useful application of DFT calculations for research and process development on the control and engineering of intrinsic point defects in Si and Ge single crystal growth from a melt are presented in focusing on (i) the difference of the dominant point defect in Si and Ge, (ii) the impact of thermal stress on intrinsic point defects in large-diameter Si crystal and (iii) the dopant impact on intrinsic point defects in Si. The results indicate that DFT calculation will be a necessary tool for the cost-effective development of the advanced crystal growth processes that will be needed for the new family of 450 mm diameter Si crystals or for V-poor, large diameter Ge crystals [1]. Besides the crystal growth, DFT calculations are also useful to for the development of “impurity gettering” technology in large-diameter Si wafers. Very recently, a C3H5 cluster ion implantation technique for proximity gettering has been reported with the low energy of around 1015/cm2 dose without recovery heat treatments. The main feature of this technique is that the gettering efficiency is higher than that by C monomer implantation, even though irradiation defects are too small to clarify by TEM observation. In the present work, we evaluate the binding energies of metal atoms with candidate gettering sites of C, H, intrinsic point defects and related complexes in Si wafers induced by C3H5 cluster ion implantation or different methods, for example, H implantation etc. by using DFT calculations. In addition to C and H atoms, we consider donor P and O atoms contained in an n- CZ-Si wafer for use in a CMOS image sensor. The simplest complexes of substitutional/interstitial C (Cs/Ci), Hi, Ps, Oi, and incorporated intrinsic point defects (vacancy (V) and self-interstitial Si (I)) by C3H5 implantation were also considered. We found that Cs-I (= Ci), Ci-Ci, Hi-I, VHn (n =1 to 3), and VO complexes are the best candidates for gettering sites. Gettering by C3H5 cluster ion implantation is more effective than that by C monomer implantation due to the formation of VHn (n = 1–3) and Hi-I complexes, which provides more effective gettering sites [2]. An approach based on statistical thermodynamics and DFT calculations to predict properties of materials composed of different types of atoms is presented. The key point of the “Hakoniwa” method is to take into account all possible structural supercells constructed by the fixed number of atoms of each species according to the composition of the target material [3]. The conservation of the total number of atoms enables calculating the average value of a material property for a given temperature by applying statistical thermodynamics to the material property values obtained for each of the possible supercells. The applications of the Hakoniwa method to the crystal growth and metal gettering are mentioned.

Combined Effect of Rapid Thermal Annealing and Crystal Nature on the Gate Oxide Reliability of Czochralski Silicon

Internal gettering (IG) of metallic impurities (MI) in Czochralski silicon (CZ-Si) is one of the key techniques in modern microelectronic engineering to manufacture high-performance devices with high process yield. Various silicon substrates such as EPI wafers with heavily boron-doped substrates, ion-implanted wafers, and rapid-thermal annealing (RTA) treated wafers have been used to enhance IG ability [1-2] and retain denuded zone (DZ) for the active area of devices. Especially, RTA-treatment is an easy way to form IG and DZ simultaneously with a rapid heat process that injects the intrinsic point defects, mainly vacancies, into the bulk. However, it was reported that vacancy clusters, or ‘nano voids’ whose size was less than 50nm [2-3] could be formed in the near-surface region after RTA process via vacancy self-trapping [4], which can possibly degrade the performance and yield of device. In this study, we investigated the effect of RTA treatment on the gate oxide reliability and their relation to the crystal nature, i.e., as-grown point defect distribution in silicon wafers.As shown in Fig. 1 a), we performed the Cu-contamination method [5] on the prepared samples to verify the crystal nature of each sample. After that, we separated the samples into two groups whether they treated by RTA or not, and carried out time-zero dielectric breakdown (TZDB) reliability tests on the patterned poly-Si/oxide/Semiconductor capacitors with the gate oxide thickness of 10 nm. As shown in Fig. 1 b), distribution of TZDB failed cell on the wafer was closely related to the crystal nature. Moreover, it was revealed that a vacancy-dominant region tends to have lower breakdown field than an interstitial-dominant region. These phenomena were only found in RTA-treated wafers and entire fail rate was drastically increases when RTA effect was combined with vacancy-dominated region, which was shown in Fig. 1 b). We assumed that as-grown vacancies contained in the vacancy-dominated region tend to enhance the supersaturation of vacancy beneath the oxide-semiconductor interface, so the formation of nano voids was accelerated and the breakdown field was lowered due to the presence of such defects. A detailed mechanism of the experimental result will be discussed. Figure 1. a) Crystal nature measured by Cu contamination method and b) TZDB frequency with or without RTP

Low Temperature Thermal Treatments for n-type Emitters on Si Solar Cells

Here we report on the impact of annealing and oxidation processes for silicon solar cells performed at low temperatures, in terms of how recombination properties at the surface and within the emitter are modified. Results from this experiment show that bulk gettering of interstitial iron impurities is also enhanced from these thermal treatments. The addition of the low temperature processes also improves the internal quantum efficiency at the short wavelengths.

A statistical model for the gettering of impurities on an atomistic scale

AbstractThe phenomena of impurities in Si in thermal equilibrium can be described on an atomistic scale. This model can statistically estimate the thermal equilibrium concentrations and the distribution of any metallic contamination atoms in advanced wafer structures if the gettering site densities in the wafer and their binding energies for the metallic impurity atoms are known. This model has the advantage that gettering phenomena can be calculated based on ab initio calculation results. Ab initio calculations indeed allow calculating the binding energy of any kind of contamination atom at any position in crystals without the need to perform extensive experiments. The model is illustrated for the gettering of Cu atoms in a p‐type Si double layer structure consisting of a moderately B‐doped layer, the “device layer,” and a heavily B‐doped layer, the “substrate.” By using this statistical approach, we can also predict Cu solubility in Si wafers for various B‐doping levels without the assumption of any solubility data in a previously‐known doping level, as is typically found in the literature. The calculated results show good agreement with published experimental observations. (© 2016 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)

Effect of grain boundary character of multicrystalline Si on external and internal (phosphorus) gettering of impurities

AbstractWe investigated the effect of the grain boundary (GB) character of multicrystalline Si (mc‐Si) on the efficiency of external and internal gettering of impurities during phosphorus diffusion gettering (PDG). We utilized seed crystals with an artificially designed GB configuration to grow mc‐Si ingots with different artificial GB characters. PDG combined with an originally developed multiple‐cycle gettering technique at low temperature was introduced on intentionally Fe‐contaminated mc‐Si samples to enhance external and internal gettering. A significant positive PDG effect was observed after PDG combined with the multiple‐cycle technique, as evidenced by the increase in lifetimes after PDG. A bright cloud‐like photoluminescence signal around contaminated GBs was observed for artificial Σ5‐GBs and tilt‐GBs after PDG, suggesting the enhancement of the internal gettering efficiency by leaving a cleaner area around the GBs. This result suggests the importance of the control of crystal defect character as well as impurities in mc‐Si ingots, which could strongly affect the PDG efficiency. Copyright © 2016 John Wiley &amp; Sons, Ltd.

Seed manipulation for artificially controlled defect technique in new growth method for quasi-monocrystalline Si ingot based on casting

We propose a new growth method for quasi-monocrystalline Si that achieves high-quality ingots and a high yield ratio. This method induces defect regions with compose dislocations surrounded by grain boundaries. These functional defects benefit the crystalline quality through impurity gettering, dislocation-propagation blocking, and stress relaxation with plastic deformation. Functional defect regions were grown from designed seeds and introduced to ingot edges where crystalline Si was disposed because of contamination. Preliminary experimentation demonstrated that functional defects could effectively form from the manipulated seeds. We call this method the Seed Manipulation for Artificially Controlled Defect Technique.

Impact of structural defect density on gettering of transition metal impurities during phosphorus emitter diffusion in multi-crystalline silicon solar cell processing

The impact of structural defect density on gettering of transition metal impurities during phosphorous emitter diffusion has been investigated using a pair of multi-crystalline silicon (mc-Si) wafers. Chromium (Cr) impurities incorporated during growth were identified by deep level transient spectroscopy (DLTS) and used to evaluate the gettering efficiency. The Cr impurity concentration in the low defect density region of mc-Si wafers was reduced from ~3.5 × 1013 cm−3 to ~1.7 × 1012 cm−3 after phosphorous diffusion gettering (PDG), while for the high defect density region, there is no appreciable variation in the Cr concentration which only changed from ~3.0 to ~2.2 × 1012 cm−3 following PDG. It was concluded that the gettering process is not effective for highly defective regions of mc-Si wafers due to the ineffective impurity release from structural defects during the PDG process. Open image in new window

Response of as grown dislocation structure to temperature and stress treatment in multi-crystalline silicon

Dislocations and dislocation networks in multi-crystalline (mc) silicon wafers for photovoltaic applications act as minority carrier recombination centers and thus limit the efficiency of solar cells. The literature shows results for a massive dislocation reduction by applying an annealing procedure in combination with and without an impurity gettering step. In this work different kinds of annealing experiments with mc silicon samples were carried out at 1200°C and 1365°C for 1h to 96h under an applied stress of up to 4.2MPa under pure inert or boron containing atmospheres. The results show clearly that, under the used process conditions, a dislocation reduction could not be observed via defect selective etching using different kinds of etchants. It was found, that it is essential to carefully select the etching solution as the electrical resistivity of the samples might change after a respective thermal treatment, such that the eventually still present dislocations will not be overseen.

Enhanced Equipment and New Processes As Enabler for Power Technologies on 300mm Substrates

Transferring power technologies from 200mm silicon substrates to 300mm provides challenges with regard to very special substrate materials, process equipment, and unit processes in addition to those faced by a similar transfer of CD driven commodity products as DRAMS and MPUs. Due to the fact that the current path leads vertically through the substrate and that the final substrate thickness thus determines the figure of merit, the electrical resistance of the device in on-state, ultra-thin wafer handling for wafer backside processing is a further specialty and hence challenge for power semiconductors manufacturing. Current furnace equipment for standard CMOS is capable of processing at temperatures up to 1000°C whereas power technologies require furnace temperatures up to 1200°C which requires hardware adaptation of the tools to comply reliably with these requirements. Some applications furthermore require temperature uniformity within very narrow intervals across the wafers within wafer batches. Wafers with polysilicon films on the wafer backside for impurity gettering are so far only available on 200mm. Such gettering films were deposited and analytically assessed with regard to their gettering capabilities. The extremely high doped wafer substrates for manufacturing power devices are not available yet from the suppliers in both sufficient quality and quantity to start 300mm power semiconductor activities. These substrates have to be manufactured by the semiconductor manufacturer by epitaxial growth. In addition to severe modifications of the epitaxial reactors and the provision of the complete infrastructure that allows running such processes under safe operation conditions unit process development is very challenging. Simultaneous achievements of both supreme uniformity of thick epitaxial layers and of the dopant distribution therein is key to allow perfect pattern generation and transfer and identical electrical device performance respectively all across the wafer until the very wafer edge to take full advantage of the productivity advantage of large diameter wafer processing. All the activities to improve tools and hence processes, were severely supported by equipment and process simulation. To boost productivity additionally to processing 300mm diameter wafers the use of a batch epitaxial tool has been envisioned for the growth of very thick and high resistivity silicon for IGBT applications. All the tool and process learning done on a 5-wafer 200mm batch tool will be used for the design and manufacturing of a similar tool type processing 300mm substrate. For this application high focus was posed on the reduction of sliplines, irregularities in film growth with atomic scale heights, resulting from non-uniform temperature coupling to the substrates in process. While critical CDs in high end products differ by almost an order of magnitude between power semiconductors and standard CD driven CMOS technologies, the tolerated CD uniformities are rather comparable. This finally requires for pattern transfer advanced plasma etch equipment with all the “knobs” to address wafer center and wafer periphery individually regarding etch rate, profile shape, and CD to achieve lowest center-edge non-uniformities. The various tool and process aspects of 300mm power semiconductor manufacturing will be addressed and reviewed in this talk. The work has been performed in the project EPT300, co-funded by grants from Austria, Germany, Italy, The Netherlands and the ENIAC Joint Undertaking.

Removal of Impurities from Metallurgical Grade Silicon During Ga-Si Solvent Refining

Purification of metallurgical grade silicon (MG-Si), using gallium as the impurity getter has been investigated. The technique involves growing Si dendrites from an alloy of MG-Si with Ga, followed by their separation by acid leaching. The morphologies of impurity phases in the MG-Si and the Ga-Si alloy were investigated during the solvent refining process. Effective segregation ratios of B and P in the Ga-Si system were calculated. Most metallic impurities formed silicides, such as Si-Fe-Ga-Mn or Si-Fe-Ga impurity phases, which segregated to the grain boundaries of Si or into the Ga phase during the Ga-Si solvent refining process. After purification, the refined Si is plate-like with crystallographic orientation, and the removal fraction of B and P was 83.28 % and 14.84 % respectively when the Si proportion was 25 % in the Ga-Si alloy. The segregation ratios of B and P were determined to be 0.15 and 0.83 when the solid fraction of Si was 0.25. The effective removal of B and P by a solidification refining process with a Ga-Si melt is clarified.

Enhanced phosphorus gettering of impurities in p-type Czochralski silicon through a variable temperature processing (VTP)

This paper investigates the effect of heat treatment with a phosphorus-rich porous silicon layer on the electrical properties Czochralski (CZ), p-type monocrystalline silicon (c-Si) wafer. Phosphorus diffusion into porous silicon layer can play a crucial role for gettering metallic impurities. Further, the variable temperature process (VTP) was presented to provide higher gettering efficiency than the constant temperature process (CTP). We estimated with a Quasi-Steady-State Photo-Conductance (QSSPC) technique the effective minority carrier lifetime values τeff. The Light-Beam-Induced-Current measurements (LBIC) have been executed to estimate the diffusion length (LD). In the I–V characteristics, we observed a significant increase in Voc and Jsc. Particularly; we can say that the VTP may be required to provide the highest efficiency in devices.

Enhanced Equipment and New Processes As Enabler for Power Technologies on 300mm Substrates

The customized substrates for manufacturing 300mm power semiconductors had to be prepared by deposition processes and epitaxial growth on standard substrates since they were not yet available from suppliers in both sufficient quality and quantity. Polysilicon films were deposited on wafer backsides and optimized regarding impurity gettering. Severe modifications of existing epitaxy reactors, the facilitation, and the infrastructure were prerequisite to develop extremely high doped, thick silicon layers with both supreme uniformity of layer thickness and dopant distribution to take full advantage of the productivity advantage of large diameter wafer processing. Simulation supporting these activities was also key to enable furnace processes with extremely tight temperature ranges. For the development of very thick, high resistivity silicon layers a 5-wafer 200mm batch tool was used to exploit the tool and process learning for the design and manufacturing of a similar 300mm batch tool. For pattern transfer the same advanced plasma etch equipment was mandatory to achieve similarly uniformities regarding etch rate, profile shape, and CD as in CD-driven advanced DRAMs and MPUs.

Porous silicon fabrication by anodisation: Progress towards the realisation of layers and powders with high surface area and micropore content

With a view to producing thick and very high surface area microporous silicon layers (and subsequently powders) by electrochemical anodisation, the incorporation of various types of chemical additives has been investigated, these in combination with hydrofluoric acid electrolyte and high-resistivity p-type parent substrates. Comparison under constant charge conditions shows that anodisation using 50 wt% hydrofluoric acid, or inclusion of the additives hydrochloric acid, sulphuric acid, or ammonium dodecylsulfate with lower concentration hydrofluoric acid, can facilitate powders with internal surface areas of up to 864 m2/g, average pore sizes in the region of 2.8–3.2 nm, and pore volumes in excess of 0.8 cm3/g – all as determined using nitrogen gas adsorption and associated isotherm analysis. Porous silicon powders with appreciable micropore content have thus been achieved, for the first time. Relevant application areas for such material are diverse, and potentially include energetics, impurity gettering, gas sensing microchips, orthopaedic implants, hydrogen storage, and Li-ion battery anodes.

Minority-carrier lifetime and defect content of n-type silicon grown by the noncontact crucible method

We evaluate minority-carrier lifetime and defect content of n-type photovoltaic silicon grown by the noncontact crucible method (NOC-Si). Although bulk impurity concentrations are measured by inductively coupled plasma mass spectroscopy to be less than one part per million, homogeneously throughout the as-grown material we observe lifetimes in the ~150µs range, well below the theoretical entitlement of single-crystalline silicon. These observations suggest the presence of homogeneously distributed recombination-active point defects. We compare an industry-standard gettering profile to an extended gettering profile tailored for chromium extraction, to elucidate potential gains and limitations of impurity gettering. Near the ingot top, gettering improves lifetimes to 750 and >1800µs for standard and extended profiles, respectively. Relatively lower gettered lifetimes are observed in wafers extracted from the ingot middle and bottom. In these regions, concentric-swirl patterns of low lifetime are revealed after gettering. We hypothesize that gettering removes a large fraction of fast-diffusing recombination-active impurities, while swirl microdefect regions reminiscent of Czochralski silicon can locally limit gettering efficiency and lifetime. Apart from these swirl microdefects, a low dislocation density of <103cm−2 is observed. The millisecond lifetimes and low dislocation density suggest that, by applying appropriate bulk microdefect and impurity control during growth and/or gettering, n-type NOC-Si can readily support solar cells with efficiencies >23%.