General Polynomial Research Articles

An Efficient Solution of Multiplicative Differential Equations through Laguerre Polynomials

The field of multiplicative analysis has recently garnered significant attention, particularly in the context of solving multiplicative differential equations (MDEs). The symmetry concept in MDEs facilitates the determination of invariant solutions and the reduction of these equations by leveraging their intrinsic symmetrical properties. This study is motivated by the need for efficient methods to address MDEs, which are critical in various applications. Our novel contribution involves leveraging the fundamental properties of orthogonal polynomials, specifically Laguerre polynomials, to derive new solutions for MDEs. We introduce the definitions of Laguerre multiplicative differential equations and multiplicative Laguerre polynomials. By applying the power series method, we construct these multiplicative Laguerre polynomials and rigorously prove their basic properties. The effectiveness of our proposed solution is validated through illustrative examples, demonstrating its practical applicability and potential for advancing the field of multiplicative analysis.

What makes for digital entrepreneurs? The role of AI-related drivers for nascent digital start-up activities

PurposeApplying the Stimulus–Organism–Response (SOR) model, this study aims to explore how AI-driven stimuli (e.g. ChatGPT adoption in entrepreneurship and perceived AI competencies) stimulate individuals’ cognitive organisms (e.g. digital entrepreneurial opportunity exploration and exploitation), and how these individually, congruently, and incongruently trigger their behavioral responses (e.g. nascent digital start-up activities).Design/methodology/approachUtilizing a sample of 1326 MBA students in Vietnam with a stratified sampling approach, multiple linear regression and polynomial regression with response surface analysis were used to test hypotheses.FindingsThe findings reveal that ChatGPT adoption in entrepreneurship and perceived AI competencies have a positive and significant impact on individuals’ digital entrepreneurial opportunity exploration and exploitation, which in turn, positively affects nascent digital start-up activities. Moreover, the study also reports that digital entrepreneurial opportunity exploration and exploitation can be congruently combined with each other to trigger the effects of nascent digital start-up activities.Practical implicationsSome valuable recommendations based on the findings have been provided for practitioners and policymakers.Originality/valueThe study contributes to the academic landscape by validating the SOR model within the context of AI adoption and entrepreneurship. It emphasizes the sequential processes of stimulus, cognitive responses, and behavioral outcomes, shedding light on nuanced effects in the digital entrepreneurial landscape.

Exploring Time Delay Interferometry ranging as a practical ranging approach in the Bayesian framework

Time Delay Interferometry (TDI) is an indispensable step in the whole data processing procedure of space-based gravitational wave detection, as it mitigates the overwhelming laser frequency noise, which would otherwise completely bury the gravitational wave signals. Knowledge on the inter-spacecraft optical paths (i.e. delays) is one of the key elements of TDI. Conventional method for inter-spacecraft ranging mainly relies on the pseudo-random noise (PRN) code signal modulated onto the lasers. To ensure the reliability and robustness of this ranging information, it would be highly beneficial to develop other methods which could serve as cross-validations or backups. This paper explores the practical implementation of an alternative data-driven approach – time delay interferometry ranging (TDIR) – as a ranging technique independent of the PRN signal. Distinguished from previous research, our TDIR algorithm significantly relaxes the stringent requirement for clock synchronization imposed by traditional TDI procedure. By framing TDIR as a Bayesian parameter estimation problem and employing a general polynomial parametrization, we demonstrate our algorithm with simulated data based on the numerical orbit of Taiji. In the presence of laser frequency noise and secondary noises, the estimated median values of delays are only 5.28 ns away from the ground truths, capable of suppressing laser frequency noise to the desired level. Additionally, we have also analyzed the requirements of mitigating optical bench noise and clock noise on TDIR, and presented an illustrative example for the impact of laser locking.

An efficient hardware accelerator for NTT-based polynomial multiplication using FPGA

An efficient hardware accelerator for NTT-based polynomial multiplication using FPGA

Skew Cyclic and Skew Constacyclic Codes over a Mixed Alphabet

In this note, we study skew cyclic and skew constacyclic codes over the mixed alphabet R=FqR1R2, where q=pm, p is an odd prime with m odd and R1=Fq+uFq with u2=u, and R2=Fq+uFq+vFq with u2=u,v2=v,uv=vu=0. Such codes consist of the juxtaposition of three codes of the same size over Fq,R1, and R2, respectively. We investigate the generator polynomial for skew cyclic codes over R. Furthermore, we discuss the structural properties of the skew cyclic and skew constacyclic codes over R. We also study their q-ary images under suitable Gray maps.

AEKA: FPGA Implementation of Area-Efficient Karatsuba Accelerator for Ring-Binary-LWE-Based Lightweight PQC

Lightweight PQC-related research and development have gradually gained attention from the research community recently. Ring-Binary-Learning-with-Errors (RBLWE)-based encryption scheme (RBLWE-ENC), a promising lightweight PQC based on small parameter sets to fit related applications (but not in favor of deploying popular fast algorithms like number theoretic transform). To solve this problem, in this article, we present a novel implementation of hardware acceleration for RBLWE-ENC based on Karatsuba algorithm, particularly on the field-programmable gate array (FPGA) platform. In detail, we have proposed an area-efficient Karatsuba Accelerator (AEKA) for RBLWE-ENC, based on three layers of innovative efforts. First of all, we reformulate the signal processing sequence within the major arithmetic component of the KA-based polynomial multiplication for RBLWE-ENC to obtain a new algorithm. Then, we have designed the proposed algorithm into a new hardware accelerator with several novel algorithm-to-architecture mapping techniques. Finally, we have conducted thorough complexity analysis and comparison to demonstrate the efficiency of the proposed accelerator, e.g., it involves 62.5% higher throughput and 60.2% less area-delay product (ADP) than the state-of-the-art design for n =512 (Virtex-7 device, similar setup). The proposed AEKA design strategy is highly efficient on the FPGA devices, i.e., small resource usage with superior timing, which can be integrated with other necessary systems for lightweight-oriented high-performance applications (e.g., servers). The outcome of this work is also expected to generate impacts for lightweight PQC advancement.

Retraining surrogate models in increasingly restricted design spaces: a novel building energy model calibration method

Surrogate (i.e. meta) models can approximate building energy models (BEMs) accurately and quickly, hence they have been widely used in BEM calibration studies. Typically, the surrogate models are trained a single time over the entire unknown building parameter space with a design such as Latin hypercube sampling. In this article, a multiple polynomial regression surrogate model is, instead, retrained with increasingly restricted designs. In each training repetition, the bounds of the design narrow around the unknown building parameter values that minimize the error between the surrogate model’s predictions and the measured energy. This ‘cascading surrogate’ calibration method finds CVRMSE values that are much lower than those of a powerful black box optimizer in a case study with simulated ‘measured’ data. However, the method has similar performance to the black box optimizer in a case study with real hourly measured energy, probably since the BEM was not configured accurately enough.

A new algorithm for computing the nearest polynomial to multiple given polynomials via weighted ℓ2,q-norm minimization and its complex extension

A new algorithm is proposed in this paper for computing the nearest polynomial to multiple given polynomials with a given zero in the real case, where the distance between polynomials is defined by the weighted ℓ2,q norm (0<q≤2). First, the problem is formulated as a univariate constrained non-convex minimization problem, where prior information of the coefficients of the polynomial can be embedded by selecting proper weights. Then, an iteratively reweighted algorithm is designed to solve the obtained problem, and also the convergence and rate of convergence are uniformly demonstrated for all q in (0,2]. Since all the existing methods for computing the nearest polynomial to multiple given polynomials with a given zero are limited to the real case, we ingeniously extend the results to the complex case. Finally, two representative examples that separately compute the nearest real and complex polynomials are presented to show the effectiveness of the proposed algorithm.

Optimization of Mg-Al Layered Double Hydroxide Film Preparation and Corrosion Resistance Study on AZ91D Mg Alloy by Multivariate Polynomial Regression Fitting.

Layered double hydroxide (LDH) films have received extensive attention for their unique physical barrier function and ion exchange properties, which make them promising candidates for corrosion protection of magnesium alloys. In this paper, we used the multiple polynomial regression fitting method to establish a regression equation for the electrochemical corrosion resistance with the reaction temperature (T), pH, and reaction time (t) of the Mg-Al LDH film on the AZ91D magnesium alloy. The goodness of fit, confidence, and residual analyses confirmed the high accuracy of the model equation. According to the calculation using the fmincon function, the best corrosion resistance of the prepared samples could be achieved when the parameters are T = 135 °C, pH = 12.0, and t = 15 h. Then, the experimental results showed that the corrosion current density (Icorr) of the obtained LDH film under the above conditions could be 1.07 × 10-7 A/cm2, approximately 3 orders of magnitude lower than the magnesium alloy substrate, after immersion in a 3.5 wt % NaCl solution for 180 h, the surface structure of the LDH film did not change significantly, and the Icorr was still 2 orders of magnitude higher than that of the magnesium alloy substrate. Hence, a synergistic effect equation for the reaction temperature, pH, and reaction time on the corrosion resistance of the LDH film on a magnesium alloy surface prepared by the hydrothermal method was obtained. Moreover, using this equation, we obtained an LDH film with good corrosion resistance and durability, providing theoretical guidance for optimizing the process of preparing the LDH film by the hydrothermal method in practical applications.

Construction and Convergence of H-S Combined Mean Method for Multiple Polynomial Zeros

Construction and Convergence of H-S Combined Mean Method for Multiple Polynomial Zeros

A Flexible Hardware Accelerator for Booth Polynomial Multiplier

This article presents a parameterized/flexible hardware accelerator design tailored for the Booth polynomial multiplication method. The flexibility is achieved by allowing users to compute multiplication operations across various operand lengths, reaching up to 212 or 4096 bits. Our optimization strategy involves resource reuse, effectively minimizing the overall area cost of the Booth accelerator design. A comprehensive evaluation compares the proposed multiplier design with several non-digitized bit-serial polynomial multiplication accelerators. Implementation is realized in Verilog HDL using the Vivado IDE tool, featuring diverse operand sizes, and post-place and route assessments are performed on the Xilinx Virtex-7 field-programmable gate array device. For the largest considered operand size of 1024 × 1024, our Booth accelerator utilizes 1434 slices and can operate on a maximum frequency of 523.56 MHz. A single polynomial multiplication operation requires 0.977 μs and the total power consumption is 927 mW. Moreover, a comparison to state-of-the-art accelerators reveals that the proposed flexible accelerator is 1.34× faster in computation time and 1.05× more area-efficient than the recent dedicated polynomial multiplication design. Therefore, the implementation results and comparison to the state of the art show that the proposed accelerator is suitable for a wide range of cryptographic applications.

Fast polynomial multiplication using matrix multiplication accelerators with applications to NTRU on Apple M1/M3 SoCs

Efficient polynomial multiplication routines are critical to the performance of lattice-based post-quantum cryptography (PQC). As PQC standards only recently started to emerge, CPUs still lack specialized instructions to accelerate such routines. Meanwhile, deep learning has grown immeasurably in importance. Its workloads call for teraflops-level of processing power for linear algebra operations, mainly matrix multiplication. Computer architects have responded by introducing ISA extensions, coprocessors and special-purpose cores to accelerate such operations. In particular, Apple ships an undocumented matrix-multiplication coprocessor, AMX, in hundreds of millions of mobile phones, tablets and personal computers. Our work repurposes AMX to implement polynomial multiplication and applies it to the NTRU cryptosystem, setting new speed records on the Apple M1 and M3 systems-on-chip (SoCs): polynomial multiplication, key generation, encapsulation and decapsulation are sped up by 1.54 – 3.07 × , 1.08 – 1.33 × , 1.11 – 1.50 × and 1.20 – 1.98 × , respectively, over the previous state-of-the-art.

TriKSV-LG: a robust approach to disease prediction in healthcare systems using AI and Levy Gazelle optimization

A seamless connection between the Internet and people is provided by the Internet of Things (IoT). Furthermore, lives are enhanced using the integration of the cloud layer. In the healthcare domain, a reactive healthcare strategy is turned into a proactive one using predictive analysis. The challenges faced by existing techniques are inaccurate prediction and a time-consuming process. This paper introduces an Artificial Intelligence (AI) and IoT-based disease prediction method, the TriKernel Support Vector-based Levy Gazelle (TriKSV-LG) Algorithm, which aims to improve accuracy, and reduce the time of predicting diseases (kidney and heart) in healthcare systems. The IoT sensors collect information about patients’ health conditions, and the AI employs the information in disease prediction. TriKSV utilizes multiple kernel functions, including linear, polynomial, and radial basis functions, to classify features more effectively. By learning from different representations of the data, TriKSV better handles variations and complexities within the dataset, leading to more robust disease prediction models. The Levy Flight strategy with Gazelle optimization algorithm tunes the hyperparameters and balances the exploration and exploitation for optimal hyperparameter configurations in predicting chronic kidney disease (CKD) and heart disease (HD). Furthermore, TriKSV's incorporation of multiple kernel functions, combined with the Gazelle optimization strategy, helps mitigate overfitting by providing a more comprehensive search space for optimal hyperparameter selection. The proposed TriKSV-LG method is applied to two different datasets, namely the CKD dataset and the HD dataset, and evaluated using performance measures such as AUC-ROC, specificity, F1-score, recall, precision, and accuracy. The results demonstrate that the proposed TriKSV-LG method achieved an accuracy of 98.56% in predicting kidney disease using the CKD dataset and 98.11% accuracy in predicting HD using the HD dataset.

A High-Throughput and Scalable Schoolbook Polynomial Multiplier for Accelerating Saber on FPGA Using a Novel Winograd-Based Architecture

A High-Throughput and Scalable Schoolbook Polynomial Multiplier for Accelerating Saber on FPGA Using a Novel Winograd-Based Architecture

Side-channel Analysis of Lattice-based Post-quantum Cryptography: Exploiting Polynomial Multiplication

Polynomial multiplication algorithms such as Toom-Cook and the Number Theoretic Transform are fundamental building blocks for lattice-based post-quantum cryptography. In this work we present correlation power-analysis-based side-channel analysis methodologies targeting every polynomial multiplication strategy for all lattice-based post-quantum key encapsulation mechanisms in the final round of the NIST post-quantum standardization procedure. We perform practical experiments on real side-channel measurements, demonstrating that our method allows to extract the secret key from all lattice-based post-quantum key encapsulation mechanisms. Our analysis shows that the used polynomial multiplication strategy can significantly impact the time complexity of the attack.

Analysis of EM Fault Injection on Bit-sliced Number Theoretic Transform Software in Dilithium

Bitslicing is a software implementation technique that treats an N -bit processor datapath as N parallel single-bit datapaths. Bitslicing is particularly useful to implement data-parallel algorithms, algorithms that apply the same operation sequence to every element of a vector. Indeed, a bit-wise processor instruction applies the same logical operation to every single-bit slice. A second benefit of bitsliced execution is that the natural spatial redundancy of bitsliced software can support countermeasures against fault attacks. A k -redundant program on an N -bit processor then runs as N/k parallel redundant slices. In this contribution, we combine these two benefits of bitslicing to implement a fault countermeasure for the number-theoretic transform (NTT) . The NTT efficiently implements a polynomial multiplication. The internal symmetry of the NTT algorithm lends itself to a data-parallel implementation, and hence it is a good candidate for the redundantly bitsliced implementation. We implement a redundantly bitsliced NTT on an advanced 667MHz ARM Cortex-A9 processor, and study the fault coverage for the protected NTT under optimized electromagnetic fault injection (EMFI) . Our work brings two major contributions. First, we show for the first time how to develop a redundantly bitsliced version of the NTT. We integrate the protected NTT into a full Dilithium signature sequence. Second, we demonstrate an EMFI analysis on a prototype implementation of the Dilithium signature sequence on ARM Cortex-M9. We perform a detailed EM fault-injection parameter search to optimize the location, intensity and timing of injected EM pulses. We demonstrate that, under optimized fault injection parameters, about 10% of the injected faults become potentially exploitable. However, the redundantly bitsliced NTT design is able to catch the majority of these potentially exploitable faults, even when the remainder of the Dilithium algorithm as well as the control flow is left unprotected. To our knowledge, this is the first demonstration of a bitslice-redundant design of the NTT that offers distributed fault detection throughout the execution of the algorithm.

CNC: A lightweight architecture for Binary Ring-LWE based PQC

In lattice-based cryptography, Ring Learning with Errors (RLWE) is a computationally hard cryptographic problem, comprising three basic mechanisms i.e., key generation, encryption, and decryption. Binary Ring Learning with Error (BRLWE), a new variant of RLWE has been proposed recently to reduce the key size and computational complexity compared to previous RLWE-based schemes. Based on this BRLWE scheme, efficient hardware architectures have been obtained in recent works for lightweight applications. The key operation involved in this scheme is AB+C , where A and C are integer polynomials and B is a binary polynomial. This paper proposes an efficient hardware architecture for BRLWE-based scheme targeted for lightweight applications. The architecture computes the arithmetic operation AB+C, which includes polynomial multiplication and addition over the polynomial ring Zq/(xn+1). The proposed architecture is applied in two conditions, fixed and variable values of q. Experimental results show the architecture proposed has 50% less Area-Delay Product (ADP) and 20% less Power-Delay Product (PDP) compared to the recently reported work for n=256.

Thermomechanical response and elastocaloric effect of shape memory alloy wires

Refrigeration technologies based on the elastocaloric effect of shape memory alloys (SMAs) have attracted much interest in recent years. To seek for schemes that can improve the temperature span and efficiency of elastocaloric devices, this work explores more practical loading conditions (between adiabatic and isothermal) of SMAs. To account for the smoothness of the martensite phase transformation of SMAs, a general polynomial form of hardening-like function is adopted in the phenomenological multi-physics coupling framework. The modeling framework is further calibrated by measurements of the thermomechanical responses of pre-trained Ni–Ti wires. Due to the hardening-like function, the martensitic volume fraction cannot be explicitly expressed. Accordingly, a new numerical scheme is also presented in this work. Moreover, an empirical function of the maximum transformation strain is proposed based on the experimental observation, which improves the capability of the model to capture experimental data. This work aims to provide a paradigm from material characterization to theoretical modeling and numerical simulation, and then to elastocaloric cooling performance analysis of SMAs.

The calibration of sharp-crested weirs with a horizontal edge used for measuring flows in partially full pipes

This paper presents the results of a laboratory study on the discharge capacity of sharp-crested weirs fitted with a horizontal edge in pipes during open-channel flow conditions and clean water used to measure the outflow. Such sharp-crested weirs are mounted in pipes and are used to control the inflow to separators. The stream profile does not correspond to the profile given by Bazin for sharp crested weirs in channels. A desired location of the water level measurement point for flow rate calculations was provided. Discharge curves were identified for three sharp-crested weirs of 0.0465, 0.0634 and 0.0771 m in height, installed in the pipe of 0.1534 m in diameter and inclinations of 0.5 and 1.0%. The discharge curves for weir flow with free nappe does not show a significant effect of the pipe slope on the weir discharge capacity. The non-dimensional formulas for the discharge capacity of the sharp-crested weir were found as general polynomial regressions. The results indicate that the calibrated sharp-crested weir with a horizontal edge placed in a pipe can be used to control the flow. Due to the scale effect, relationships obtained from the calibration cannot be generalised to other pipe diameters and weirs heights than those analysed.

Finding Galois splitting models to compute local invariants

For prime p and small n, Jones and Roberts have developed a database recording invariants for p-adic extensions of degree n. We contributed to this database by computing the Galois slope content, Galois mean slope, and inertia subgroup for a variety of wildly ramified extensions of composite degree using the idea of Galois splitting models. We will describe a number of strategies to find Galois splitting models including an original technique using generic polynomials and Panayi's root finding algorithm.