Interface Defect Generation Research Articles

O2 and Ar plasma processing over SiO2/Si stack: Effects of processing gas on interface defect generation and recovery

Defect generation and recovery at the interface of a silicon dioxide/silicon (SiO2/Si) stack are studied in oxygen (O2) or argon (Ar) plasma processing and post-annealing. Defect generation is recognized to be dependent on the processing gas and the SiO2 layer thickness. O2 plasma processing shows a strong incident-ion energy dependence, where ion’s implantation, diffusion, and reactions in the SiO2 layer play important roles in defect generation. A similar dependence is observed for Ar plasma processing; however, it also shows the photon effects in defect generation for a thick SiO2 layer. Defect recovery is demonstrated by annealing, where recovery depends on the annealing temperature as well as the amount of defects generated at the interface.

Investigation of degradation behavior under negative bias temperature stress in Si/Si0.8Ge0.2 metal-oxide-semiconductor capacitors

In this paper, capacitance and conductance characteristics are used to explain reliability issues in metal-oxide-semiconductor capacitors (MOSCAPs) with a silicon-germanium (SiGe) channel. The SiGe channel devices are also comprehensively compared to traditional Si channel devices. After negative bias temperature stress, both exhibit flat-band voltage (V FB) shifts in the negative direction and a rise in the conductance hump. Generally, the process of Si devices is more stable than SiGe devices, resulting in the interface quality of Si MOSCAPs being better due to lattice constant matching at the interface. However, it is noteworthy that the degradation of Si MOSCAPs is more serious than that of Side MOSCAPs. Therefore, this study quantitatively extracts the interface defects and illustrates the generation of interface defects with a reaction-diffusion model. In addition, the difference in the injected energy level is used to explain the difference in the VFB shift.

Charging Effects in Al-SiO2-p-Si Structures After Low-Energy Electron Beam Irradiation

The effect of electron beam irradiation on trap charging and interface defect generation in Al/SiO2/Si structures was investigated by high-frequency capacitance–voltage measurements. Irradiation was carried out with two beam energies, at which the electron penetration depth was smaller and larger than the SiO2 thickness. The effect of applied bias, which changes the electric field inside the SiO2 film and the Si surface potential, on both the interface defect generation under the electron beam irradiation and their annealing was revealed. This showed that excess electrons generated by an e-beam play an important role in the interface defect formation. It was found that interface trap relaxation can occur even at room temperature, likely by electron tunneling from Si or hole tunneling from SiO2. The relaxation of positive bulk charge occurs at temperatures higher than 400 K via thermally stimulated carrier escape from traps. The activation energy for this process was estimated as 0.35–0.4 eV.

Interface reaction kinetics in SiGe oxidation

The oxidation of SiGe is very different from that of Si or Ge, leading to poor interface quality in oxidized SiGe gate stacks. In this work, SiGe oxidation kinetics and its effects on the generation of interface defects are discussed by considering the GeO desorption as well as Ge precipitation. Unlike GeO2/Ge, no GeO desorption associated with the reaction between GeO2 and Ge is detected in GeO2/SiGe below 700 °C. Instead, GeO desorption related to a reaction between GeO2 and Si is observed above 800 °C; however, it is suppressed by inserting a thin SiO2 layer on the SiGe surface. Based on experimental results and thermodynamic calculations, the SiGe oxidation kinetics is reconsidered in conjunction with the interface properties in SiGe gate stacks. The present results provide clear insights into a viable solution for high performance SiGe gate stacks.

Two-dimensional defect mapping of the SiO2/4H−SiC interface

Current generations of 4H-SiC metal-oxide-semiconductor field-effect transistors are still challenged by the high number of defects at the SiO2/SiC interface that limit both the performance and gate reliability of these devices. One potential source of the high density of interface defect states (D-it) is the stepped morphology on commonly used off-axially grown epitaxial surfaces, favoring incomplete oxidation and the formation of defective transition layers. Here we report measurements on intentionally modified 4H-SiC surfaces exhibiting both atomically flat and stepped regions where the generation of interface defects can be directly linked to differences in surface roughness. By combining spatially resolving structural, chemical, optical, and electrical analysis techniques, a strong increase of D-it for stepped surfaces was revealed while regions with an atomically flat SiC surface exhibited close-to-ideal interface properties.

Passivation of SiO2/4H–SiC interface defects via electron cyclotron resonance hydrogen–nitrogen mixed plasma pretreatment for SiC surface combined with post-oxidation annealing

We proposed an electron cyclotron resonance microwave hydrogen–nitrogen mixed plasma (HNP) pretreatment for 4H–SiC surface combined with post-oxidation annealing (POA) to improve the SiO2/SiC interface properties. Results revealed that HNP surface pretreatment effectively reduced the density of interface traps (Dit), which was closely correlated with interface flattening because of surface flattening, surface state (contaminants, adsorbates, and dangling bonds) reduction, and suppressed generation of interface defects during oxidation. Combined with POA, Dit was further decreased because of passivation of the formed defects after oxidation. The correlation among passivation, SiC surface properties, SiO2/SiC interface properties, and defect levels was established.

Study on Structural, Mechanical, and Optical Properties of Al2O3–TiO2 Nanolaminates Prepared by Atomic Layer Deposition

Structural, optical, and mechanical properties of Al2O3/TiO2 nanolaminates fabricated by atomic layer deposition (ALD) were investigated. We performed transmission electron microscopy (TEM), X-ray diffraction (XRD), X-ray reflectivity (XRR), energy dispersive X-ray spectroscopy (EDX), ellipsometry, UV–vis spectroscopy, photoluminescence (PL) spectroscopy, and nanointendation to characterize the Al2O3/TiO2 nanolaminates. The main structural, optical, and mechanical parameters of Al2O3/TiO2 nanolaminates (thickness, grain size, refractive index, extinction coefficient, band gap, hardness, and Young’s module) were calculated. It was established that with decreasing of the layer thickness, the value of band gap energy increases due to the quantum size effect related to the reduction of the nanograins size. On the other hand, the decreasing of nanograins size leads to generation of interface defects and, as a consequence, to the increasing of Urbach energy. It was also shown that there is an interdiffusion lay...

Control of SiO2/Si interface defects generation during thin dielectric film etching using CHxFy/Ar/O2 plasma

We investigated the quantitative control of SiO2/Si interface defects caused by CHxFy/Ar/O2 plasma etching. Both the number and the cause of interface defects generation strongly depended on the residual thicknesses of SiO2. When the residual thickness becomes small, in addition to the VUV/UV irradiation, ion injection caused a remarkable increase in the number of interface defects associated with Si dislocation. Complete recovery from damage was difficult by low-temperature thermal annealing, especially ion-induced damage. Ion-induced damage was suppressed by controlling the residual thickness of SiO2 to be larger than the ion penetration depth. VUV/UV-induces damage could be effectively suppressed by using a light shield layer such as SiN. Moreover, VUV/UV-induces damage under a fine space pattern is expected to be suppressed in comparison with a wide-open pattern. Thus, the process design of a film stack, pattern, etching condition, and thermal annealing condition are important for controlling SiO2/Si interface defect generation during plasma processing.

(Invited) Reliability of SiGe HBTs in Long-Term Operation

Introduction In the ongoing development towards RF circuits with still higher operation frequencies SiGe HBT technologies continuously have to prove their competitiveness against advanced Si CMOS and compound semiconductor millimeter-wave circuits. Yet, besides excellent RF performance at circuit operation frequencies – meanwhile even well beyond 100 GHz –customer focus is also put on operating constraints (“safe operating area”, SOA) and long-term reliability of the devices.If the HBT power load in a circuit stays within the SOA limits but collector voltage surpasses open-base breakdown voltage (BVCEO) or the emitter-base (EB) diode is reverse biased a gradual decrease of the HBT current gain (“beta ageing”) can usually be observed (Fig. 1a). This beta degradation is correlated to an increase of the base recombination current caused by recombination centers (“traps”) at dielectric interfaces. These again are being created by hot carrier injection (“HCI”).This interface trap generation and the gradual character of ageing are in contrast with device failure of III-V devices where defects are generated inside the semiconductor and failure shows more abrupt and end-of-life characteristics [1].Concerning HBT reliability the questions to address then are: What is the maximum HBT beta degradation tolerable for any specific circuit operation? Will it stay within this limit during the anticipated circuit life-time (up to 20 years for space applications)? Our intention therefore was to develop an ageing function which describes base current change or beta degradation, respectively, as function of electrical stressors, ambient temperature, and stress time. The experimental setups to evaluate ageing are forward and reverse bias stress conditions which we applied for up to 1000h and in a temperature range from -40°C up to 150°C. Operation Constraints The SOA to which device operation should be restricted can be derived from the common-base output characteristics which indicate device instabilities by current pinch-in or electro-thermal runaway. For low-voltages electro-migration will define maximum current densities. The latter can to be avoided be defining proper design guidelines for the metal line layout. Interface Defect Generation and Annihilation Even within SOA sufficiently high electrical fields in the collector-base (CB) space charge region will trigger avalanche carrier multiplication there and part of them will be accelerated towards EB and CB spacer oxides interfaces (HCI). Subsequently, interface traps will be created by de-passivation of Si dangling bonds. Trap density is expected to evolve as Nit ~ tα with α ≈ 0.25 [2] as long as the reaction is far from saturation (i.e. trap density becomes comparable to the total areal density of interface dangling bonds). Contrary, thermal activated hydrogen re-passivation of traps leads to beta recovery. Electrical Stress and Annealing Tests Currently, two types of electrical stress tests have been established as basis for SiGe HBT reliability evaluation:Forward “mixed-mode” (MM) stress with applied VCB,stress > BVCEO and forced emitter current density JE,stress up to a few times the value corresponding to peak-fT,“REV” stress with reverse biased BE junction. Additionally, to study defect annealing we applied a combination of high current and VCB,stress > BVCEO at ambient temperatures up to 150°C to achieve junction temperatures well above 200°C. Figure 1a shows as an example the impact of 100 h REV stress and subsequent anneal on a HBT with 250 GHz peak-fT from IHP’s 0.13 µm BiCMOS technology [3]. At VBE = 0.7 V over 90% beta reduction can be observed during reverse stress (2) but annealing with junction temperature reaching 300°C lead to almost complete beta recovery (3). Ageing Function The additional trap recombination saturation currents have been evaluated as function of the relevant stressors [4]IBEr,MM = f(VCB,stress, IE,stress, Tambient)·tα IBEr,REV = f(VEB,stress, Tambient)·tα and can be added to the according compact model base current. Figure 1b shows for example base current increase as function of VEB,stressafter 100h of REV stress. This ageing function can be used to predict HBT ageing and its impact on circuit performance during circuit life cycle.

(Invited) Effect of SOI Substrate on CMOS Devices Reliability

The growing demand on low power applications as well as the continuous scaling down of CMOS devices is facing strong physical limitation, among which the control of short channel effect. In the past decade, silicon industry made several drastic changes in CMOS architecture such as integration of copper interconnect, use of nitride gate oxide dielectrics, and its subsequent replacement by Hafnium silicate as gate dielectrics, use of epitaxial SiGe etc… Use of Silicon On Insulator substrates has been used for specific applications (Application processor, RF, Photonics) but not for mainstream application. ST Microelectronics successfully developed and brought to the mass production maturity level for the very first time a fully depleted SOI platform [1,2]. In this paper we will review the mains consequences of the integration of buried oxide on CMOS device reliability, since the presence of BOX under CMOS devices has already been largely referred in the literature as being responsible for parasitic self-polarization, or unwanted joule heating with negative impact on device reliability. First the reliability of BOX itself will be reviewed, BOX interface defect generation will be analyzed, then the used of body bias polarization on transistor degradation mechanisms (time dependent breakdown, negative bias temp instability, hot carrier injection) will be presented with a special focus on hci reliability and its dependence on body bias polarization.Performance of FDSOI technology:FDSOI (Fully Depleted SOI, Figure 1) technology process has been evidenced as very attractive for low power application due to the very good control of short channel effects and very good isolation of neighboring devices. Besides, the use of undopped channel improves mobility in the channel mobility as well as device matching. Finally, the proposed architecture allows a wide range of operation back bias and the possibility to adapt the device performance or power consumption dynamically with very limited reliability penalty regardless the performance gain.Burried oxide reliabilityBuried Oxide reliability was characterized by means of linear voltage ramp stress constant voltage stress. Breakdown voltage is found above 30V, and time to breakdown having several decades of margin at operating voltage (figure 2). Besides, transistor parameters drift under back bias stress occurs above 20V and also exhibit large lifetime margins (Figure 3).MOS device reliabilityA direct comparison of 28nm bulk vs 28nm SOI technology shows that gate dielectrics related failure modes (time dependent breakdown and transistor parameter drift under vertical electrical field and / or hot carrier injection) are un-affected by the presence of buried oxide (Figure 4), since the vertical electrical field and gate stack composition are the same. At the same time, we also evidenced that additional back bias does not influence on tddb and BTI (Figure5). This finding is consistent with screening of applied back bias by the inversion layer. Additionally, we analyzed electrical defect signature to track the defect generation on the channel back-side[3,4]. It was found that in extreme back bias configuration only (>4-6V), defects can be generated at bottom interface. We also reported a full characterization of Tsi (figure 6) and back bias (figure 7) effect on HCI defect generation confirming the primary effect of carrier energy over carrier density giving a comprehensive framework to the general behavior of 28FDSOI performance-reliability trade-off (figure 8).Conclusions28nm FDSOI devices were submitted to electrical reliability. Intrinsic buried oxide reliability as well as effect of Tsi and Vb on transistors failure mode were quantified to be implemented in circuit simulators.

(Invited) Effect of SOI Substrate on CMOS Devices Reliability

In this paper we will review the mains consequences of the integration of buried oxide on CMOS device reliability, since the presence of BOx under CMOS devices has already been largely referred in the literature as being responsible for parasitic self-polarization, or unwanted joule heating with negative impact on device reliability. First the reliability of BOx itself will be reviewed, BOx interface defect generation will be analyzed, then the used of body bias polarization on transistor degradation mechanisms (time dependent breakdown tddb, negative bias temp instability NBTI, hot carrier injection HCI) will be presented with a special focus on hci reliability and its dependence on body bias polarization

Wavelength Dependence of Photon-Induced Interface Defects in Hydrogenated Silicon Nitride/Si Structure during Plasma Etching Processes

The wavelength dependence of SiNx:H/Si interface defect generation caused by vacuum ultraviolet (VUV)/UV radiation from plasma etching processes was investigated. VUV radiation (λ< 200 nm) had almost no impact on the generation of defects at the SiNx:H/Si interface, since all the radiation in this wavelength range was absorbed in the upper SiNx:H film. However, UV radiation (200 < λ< 400 nm) was able to reach the underlying SiNx:H/Si interface and damage the interface. Direct UV radiation reaching the SiNx:H/Si interface dissociated the chemical bonds at the interface and generated interface-trapped charges. The estimated total energy of absorbed photons (Etotal; 200 < λ< 400 nm) at the interface layer seems to be proportional to the interface-trapped charge density (Dit) measured by capacitance–voltage measurement. However, the mechanism underlying the relationship between Etotal and Dit is not yet clear. Visible radiation (λ> 400 nm) had no influence on damage generation on the SiNx:H/Si structure, since the visible radiation was transmitted through upper SiNx:H film and underlying interface layer. The results revealed that UV radiation transmitted through the upper dielectrics can cause the electrical characteristics of underlying metal–oxide–semiconductor (MOS) devices to fluctuate.

Fabrication of high aluminium containing rare-earth doped fiber without core–clad interface defects

The unwanted core–clad interface defect generation and related scattering loss in rare-earth doped optical fibers containing Al-oxide is up to now an unsolved problem as it cannot be avoided without modifying fiber design or composition. Here a simple technique is proposed to eliminate the problem without affecting fiber parameters. The method comprises addition of fumed silica in appropriate amount under dispersed condition to the soaking solution containing Al and rare-earth salts during the solution impregnation stage. This facilitates the networking between Al 2O 3 and SiO 2 during sintering. The method leads to an improvement in optical properties of the fibers and enables doping of high concentration of Al-oxide even in presence of GeO 2 in the core.

Effect of the Interfacial $\hbox{SiO}_{2}$ Layer in High-$k$$ \hbox{HfO}_{2}$ Gate Stacks on NBTI

A relative contribution of the interface and bulk dielectric defects to negative bias temperature instability (NBTI) in the metal/HfO2/SiO2 gate stacks was investigated. Interface trap generation was assessed by the direct-current current-voltage (DCIV) technique, which independently measures the interface defect density from bulk oxide charges and delineates the contribution of the interface defect generation to the overall NBTI measured by the threshold voltage shift (DeltaVTH). The metal/high-fc induced traps in the interfacial SiO2 layer were found to control the fast transient trap charging/generation processes, which affect the power-law exponents of DeltaVTH and the stress-generated interface trap density DeltaDIT stress time dependencies. Similar kinetics of the long-term DeltaVTH(t) and DeltaDIT(t) dependencies in the high-fe and SiO2 gate stacks suggests that the degradation is governed by the same mechanism of trap charging/generation in the SiO2 film. The investigation leads to a novel methodology for the time-to-failure (TTF) extrapolation, in which the measured DeltaVTH and DeltaDIT values are adjusted for the contributions from the fast transient defect charging/generation processes. It is shown that the conventional TTF analysis might greatly overestimate TTF. Post-NBTI stress recovery at zero relaxation voltage measured by the DCIV method showed that oxide charges and interface traps relax at the same rate indicating that the interface processes may dominate DeltaVTH relaxation. At positive relaxation voltages, however, the oxide charge relaxation exhibits a fast transient component. Relaxation at positive bias also shows an as yet unexplained fast component in the interface trap recovery.

Applications of DCIV method to NBTI characterization

The DCIV method was applied to investigate negative bias temperature instability (NBTI) in SiO 2 gate oxides. The DCIV technique, which measures the interface defect density independently from bulk oxide charges, delineates the contribution of the interface defect generation to the overall NBTI measured by the threshold voltage shift, Δ V TH. The DCIV results obtained during both stress and relaxation phases are generally consistent with the main features of the reaction–diffusion (R–D) model, which suggests positive charge generation/annealing at the Si/SiO 2 interface due to breaking/re-passivation of the Si–H bonds. These results are in agreement with the spin-dependent recombination (SDR) experiments, which reflect the density of the Si dangling bonds at the Si/SiO 2 interface ( P b centers) and its vicinity ( E′ centers). Comparison of degradation kinetics as measured by DCIV, charge-pumping, and I D − V G (Δ V TH) techniques, however, suggests that Δ V TH includes additional contributions, most likely from the oxide bulk charges. For comparison, an NBTI study was also performed on the high-k HfO 2/SiO 2 gate stacks. After adjusting for the high-k related contribution, similar kinetics of the long-term stress interface trap generation was observed in SiO 2 and high-k gate stacks suggesting a common mechanism of the interface degradation.

Interface defect generation probed by low voltage stress induced leakage current

Conduction behavior of n-MOSFET capacitors with ultra-thin oxides was investigated before and after constant current stress. It was found that stress induced leakage current (SILC) strongly depends on the low sense voltages. Conduction mechanism of the low voltage SILC (LV-SILC) was analyzed systematically, based on the assumption that the LV-SILC is due to interface trap-assisted tunneling process (ITAT). Using the LV-SILC as a probe, generation of interface defects was investigated. Defects at both interfaces of anode and cathode are involved in ITAT process. Defect generation is a nonlinear process. Dependence of defect generation rate as a function of stress time could be used as a detector of oxide breakdown.

Low voltage stress-induced leakage current as a probe of interface defects and a monitor of the oxide reliability

Conduction behaviour of n-MOSFET capacitors with an oxide thickness (Tox) of 18.5 Å was investigated before and after constant current stress. It was found that stress-induced leakage current (SILC) strongly depends on the low sense voltages. Conduction mechanism of the low voltage SILC (LV-SILC) was analysed systematically, based on the assumption that the LV-SILC is due to interface trap-assisted tunnelling (ITAT) process. Using the LV-SILC as a probe, the generation of interface defects was probed by the LV-SILC. Interface defects in both anode and cathode are involved in the ITAT process, but the former dominates the oxide reliability. Based on the results of interface defect generation sensed by the LV-SILC, a new method to project lifetime (TBD) or monitor the oxide reliability was set up.

Model for defect generation at the (1 0 0)Si/SiO2 interface during electron injection in MOS structures

The generation of interface defects during the injection of electrons in metal-oxide–semiconductor (MOS) structures with thin SiO2 gate layers and SiO2/ZrO2 gate stacks is investigated. A model is proposed to explain the kinetics of interface defect generation, based on the depassivation of trivalent silicon dangling bonds (Si3SiH→Si3Si) at the (100)Si/SiO2 interface by the injected electrons. A gaussian spread for the activation energy Ed related to the dissociation of the SiH bond is included in this model. Comparison with experimental results reveals that the mean value of the activation energy Edi decreases linearly with the electric field Eox across the SiO2 layer. This behaviour is attributed to the alignment of the Si–H dipole moment with respect to Eox, which favours the dissociation of the SiH bond.

Model for interface defect and positive charge generation in ultrathin SiO2/ZrO2 gate dielectric stacks

The generation of interface defects and positive charge during the injection of electrons in p-Si/SiO2/ZrO2/TiN structures is investigated. The kinetics of generation of both type of defects are found to be very similar. A model is proposed to explain the interface defect generation, based on the depassivation of trivalent silicon dangling bonds (Si3≡SiH→Si3≡Si⋅) at the (100)Si/SiO2 interface by the injected electrons. A Gaussian spread for the activation energy Ed related to the dissociation of the Si–H bond is included in this model. Comparison with experimental results reveals that the mean value of the activation energy Edi decreases linearly with the electric field Eox across the SiO2 layer. This behavior is attributed to the alignment of the Si–H dipole moment with respect to Eox, which favors dissociation of the Si–H bond. The hint of a correlation between the interface defect and positive charge generation suggests that the positively charged centers might be hydrogen-induced overcoordinated oxygen centers.

Defect generation and breakdown of ultrathin silicon dioxide induced by substrate hot-hole injection

Hole-induced bulk and interface defect generation and breakdown in ultrathin silicon dioxide (2.0 and 3.0 nm) are studied using substrate hot-hole injection. The results show that although these substrate hot holes are effective in creating electrically active damage in the dielectrics, these defects are very ineffective in causing breakdown as compared to those defects created by constant voltage tunneling stress. Identical to hole trapping in thicker oxides, substrate hot-hole defect generation was independent of electric field, decreased with decreasing thickness, and increased with decreasing temperature. The defect generation and breakdown of ultrathin oxides by substrate hot-hole stress is significantly different from that observed for constant voltage tunneling stress. The results suggest that the degradation and breakdown of ultrathin silicon dioxide cannot be explained by the trapping of hot holes alone.