Effect of the Interfacial $\hbox{SiO}_{2}$ Layer in High-$k$$ \hbox{HfO}_{2}$ Gate Stacks on NBTI

Abstract

A relative contribution of the interface and bulk dielectric defects to negative bias temperature instability (NBTI) in the metal/HfO2/SiO2 gate stacks was investigated. Interface trap generation was assessed by the direct-current current-voltage (DCIV) technique, which independently measures the interface defect density from bulk oxide charges and delineates the contribution of the interface defect generation to the overall NBTI measured by the threshold voltage shift (DeltaVTH). The metal/high-fc induced traps in the interfacial SiO2 layer were found to control the fast transient trap charging/generation processes, which affect the power-law exponents of DeltaVTH and the stress-generated interface trap density DeltaDIT stress time dependencies. Similar kinetics of the long-term DeltaVTH(t) and DeltaDIT(t) dependencies in the high-fe and SiO2 gate stacks suggests that the degradation is governed by the same mechanism of trap charging/generation in the SiO2 film. The investigation leads to a novel methodology for the time-to-failure (TTF) extrapolation, in which the measured DeltaVTH and DeltaDIT values are adjusted for the contributions from the fast transient defect charging/generation processes. It is shown that the conventional TTF analysis might greatly overestimate TTF. Post-NBTI stress recovery at zero relaxation voltage measured by the DCIV method showed that oxide charges and interface traps relax at the same rate indicating that the interface processes may dominate DeltaVTH relaxation. At positive relaxation voltages, however, the oxide charge relaxation exhibits a fast transient component. Relaxation at positive bias also shows an as yet unexplained fast component in the interface trap recovery.