Two-dimensional defect mapping of the SiO2/4H−SiC interface

Abstract

Current generations of 4H-SiC metal-oxide-semiconductor field-effect transistors are still challenged by the high number of defects at the SiO2/SiC interface that limit both the performance and gate reliability of these devices. One potential source of the high density of interface defect states (D-it) is the stepped morphology on commonly used off-axially grown epitaxial surfaces, favoring incomplete oxidation and the formation of defective transition layers. Here we report measurements on intentionally modified 4H-SiC surfaces exhibiting both atomically flat and stepped regions where the generation of interface defects can be directly linked to differences in surface roughness. By combining spatially resolving structural, chemical, optical, and electrical analysis techniques, a strong increase of D-it for stepped surfaces was revealed while regions with an atomically flat SiC surface exhibited close-to-ideal interface properties.