Interface defect generation probed by low voltage stress induced leakage current

Abstract

Conduction behavior of n-MOSFET capacitors with ultra-thin oxides was investigated before and after constant current stress. It was found that stress induced leakage current (SILC) strongly depends on the low sense voltages. Conduction mechanism of the low voltage SILC (LV-SILC) was analyzed systematically, based on the assumption that the LV-SILC is due to interface trap-assisted tunneling process (ITAT). Using the LV-SILC as a probe, generation of interface defects was investigated. Defects at both interfaces of anode and cathode are involved in ITAT process. Defect generation is a nonlinear process. Dependence of defect generation rate as a function of stress time could be used as a detector of oxide breakdown.