Binary Sequence Generator Research Articles

Proposal for ultrafast all-optical pseudo random binary sequence generator using microring resonator-based switches

An all-optical pseudo-random binary sequence (PRBS) generator is designed and simulated employing micro-ring resonators (MRRs) as the core technology. The PRBS generator consists of serially connected D flip-flops realized with double-bus MRR-based switches that exploit two-photon absorption induced in a pump-probe configuration, and of a MRR-based feedback XOR gate whose design is simpler than previously reported. The expected operation is theoretically validated for 3-bit and 4-bit degree PRBS generators and can be extended to higher PRBS orders with the straightforward addition of extra MRR-based D flip-flops. The MRR critical parameters, including radius, coupling coefficient and detuning, are optimized against performance metrics through numerical simulation at 250 Gb/s. The selection of these parameters according to the derived specifications can render feasible the practical implementation of the scheme and its exploitation for all-optical signal processing purposes.

A 15-Gb/s 0.0037-mm² 0.019-pJ/Bit Full-Rate Programmable Multi-Pattern Pseudo-Random Binary Sequence Generator

This brief presents a compact low-power programmable multi-pattern pseudo-random binary sequence (PRBS) generator. It is capable of producing 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> - 1, 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">15</sup> - 1, 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">23</sup> - 1 and 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">31</sup> - 1 test patterns to meet multiple testing requirements. To reduce power and area, the full-rate architecture with the truly-single-phase clock logic (TSPC) D-flip-flops (DFF) instead of the current-mode logic (CML) DFF is adopted. The multiplexer (MUX) merged TSPC DFF is proposed to avoid the delay of the MUX in conventional multiple pattern PRBS generators. Hence, the critical path delay is reduced, and thus, the maximum data rate can be improved. Fabricated in a 40-nm CMOS process (260-GHz <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> f_T</i> ), this PRBS occupies a core active area of 0.0037 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and operates at a maximum data rate of 15 Gb/s. The measured power consumption is 8.778 mW with 1.1-V supply. The figure-of-merit (FoM) is 0.019 pJ/bit at the pattern length of 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">31</sup> - 1.

Generation of Binary Sequences of Length 10230 Bits Having Better Odd and Even Correlation with Large Linear Complexity for Use in Global Navigation Satellites Systems (GNSS) Applications

Generation of Binary Sequences of Length 10230 Bits Having Better Odd and Even Correlation with Large Linear Complexity for Use in Global Navigation Satellites Systems (GNSS) Applications

Efficient Generation of Low Autocorrelation Binary Sequences

Simple and efficient algorithm based on heuristic search by shotgun hill climbing to construct binary sequences with small peak sidelobe levels (PSL) is suggested. The algorithm is applied for generation of binary sequences of lengths between 106 and 300. Improvements are obtained in almost half of the considered lengths while for the rest of the lengths, binary sequences with the same PSL values as reported in the state-of-the-art publications are found.

Entropy and Randomness: From Analogic to Quantum World

This work is dedicated to the construction and evaluation of random number generators used in cryptography. The critical element on which the security of information is based is the cryptographic key (usually a binary sequence). In order to be resistant to brute force attacks it is necessary that it be made up of random variables with a certain degree of randomness and independence. Formally, this comes back to generate the cryptographic key through the systems which ensures a certain minimum level of entropy. The observer has access to a sample, of a certain size, and based on it he will estimate the minimum value of the entropy, in the situations in which the variables resulting from the measurement process are independent. In the situation where these variables are not independent, complex mathematical procedures also allow estimation of the minimum entropy. This article is a review of how mathematical entropy can be estimated and evaluated, of the construction mode (from technologies based on analogue procedures: thermal noise in a transistor to modern procedures: quantum devices), as well as to evaluate the security of binary sequence generators used for generating cryptographic keys or critical security parameters related to new technologies based on quantum principles. The techniques and methods used to generate binary random values as well as the methods of statistical and informational validation (Shannon entropy) are exemplified in this paper.

Chaotic Binary Sequence Generator based on Logistic Map

Pseudorandom binary sequences find various applications in different areas such as security, communication, steganography and cryptography. The properties like sensitivity to initial condition, ergodicity, mixing property and dynamic behavior are used in the designing of random number generators known as chaotic systems. In this study, an efficient chaotic binary sequence generator using logistic map is proposed, implemented and analyzed. The proposed binary sequence generator generates 50 chaotic sequences by varying initial condition with fixed system parameter. Subsequently, the generated sequences are transformed to binary sequences using thresholding method. The output of binary sequences is statistically tested with FIPS 140-2 test suite in order to identify the specific properties expected for truly random binary sequences. The experimental results prove that the generated binary sequences possess identical characteristics of true random numbers and can pass all tests of FIPS 140-2 test suite.

A 1-pJ/bit 80-Gb/s $2^{15}-1$ PRBS Generator With a Modified Cherry–Hooper Output Driver

An 80-Gb/s $2^{15}-1$ pseudorandom binary sequence (PRBS) generator suitable for testing binary communication systems is presented. Implemented in a 130-nm SiGe process, the circuit is optimized for low power dissipation. For the core functionality, an energy efficiency of 1 pJ/bit is achieved, which is one of the best values among comparable published designs. In addition, the improvement of the output signal in time domain and frequency domain is targeted. The key factors affecting an ideal PRBS spectrum are identified and addressed from the system and circuit point of view. This results in spur suppression of higher than 40 dB, which is 15 dB better than previously reported works exceeding 40 Gb/s. As an output driver, a modified Cherry–Hooper amplifier is chosen. A parametrized design methodology for obtaining Bessel response is introduced and the amplifier is optimized for low power operation. Measurement results show a single-ended output signal with over 300-mV eye opening, 0.6-ps rms jitter, and a signal-to-noise ratio better than 10.5 at 80 Gb/s, which is the best-in-class output eye diagram for a PRBS generator, to the best of our knowledge.

A Critical Analysis of ECG-Based Key Distribution for Securing Wearable and Implantable Medical Devices

Wearable and implantable medical devices (WIMDs) perform critical health monitoring and therapeutic functions. However, current WIMD products lack security safeguards to protect patients from fatal cyber attacks. In the recent past, electrocardiogram (ECG) signals-based security techniques have been widely explored to secure such devices by using two cryptographic primitives, the fuzzy commitment and the fuzzy vault, respectively. Nonetheless, differences, as well as similarities between these two primitives, have not been well investigated, making it difficult to decide which one would be appropriate for a particular setting. In this paper, we perform a critical analysis on both primitives and discuss their merits and drawbacks in the context of the ECG-based key distribution. We analyze the critical challenges within each primitive-based key distribution technique, such as binary sequence generation and polynomial computations. Experimental results show that the technique based on the fuzzy commitment has a better false acceptance rate due to the randomness of ECG binary sequences. On the other hand, the fuzzy vault based scheme can achieve an acceptable false reject rate (5%) with less cost to the WIMDs. Future research is suggested to enhance the precision of ECG signal processing, to improve the efficacy of binary sequence generation process as well as to suggest ways to reduce polynomial computations.

Wideband Sparse Signal Acquisition Based on Serial Multi-Coset Sampling

Traditional parallel multi-coset sampling (MCS), which has several sub-Analog-to-Digital-Converters (sub-ADCs) working parallelly, is an attractive sub-Nyquist sampling technique for wideband sparse signals. However, the mismatch among sub-ADCs in traditional parallel MCS, such as bias, gain, and timing skew mismatch, degrades the signal acquisition performance greatly. In this paper, a serial MCS scheme based on clocking single ADC with nonuniform clock is proposed. The nonuniform sampling clock is generated by a pseudo-random binary sequence generator. An additional Sample/Hold (S/H) is used to improve the analog bandwidth of the serial MCS. Moreover, universal sampling pattern is designed for the proposed serial MCS. The sampling pattern design should not only maximize the Kruskal rank of compressed sensing matrix but also take the ADC’s sub-Nyquist sampling rate into consideration. Numeral experiments are presented demonstrating that the mismatch among sub-ADCs in traditional parallel MCS degrades the reconstruction performance greatly, and the proposed serial MCS can avoid the mismatch tactfully.

A 65-nm 10-Gb/s 10-mm On-Chip Serial Link Featuring a Digital-Intensive Time-Based Decision Feedback Equalizer

A digital-intensive on-chip serial link achieving a 10 Gb/s data rate over a 10-mm interconnect was demonstrated in a 65-nm GP process. A three-tap half-rate feed-forward equalizer was implemented for signal pre-emphasis in the transmitted block. On the receiver (RX) side, a two-tap half-rate time-based decision feedback equalizer was employed to cancel out inter-symbol interference noise. A 215 – 1 pseudorandom binary sequence generator and an in situ bit error rate (BER) monitor were designed for bit stream generation and convenient eye-diagram measurements. The measured energy efficiency of the transmitter and RX was 31.9 and 45.3 fJ/b/mm, respectively, for a data rate of 10 Gb/s. A BER less than 10−12 was verified for an eye width of 0.43 unit interval.

An Optical Duobinary Downlink Access Scheme Using Low Pass Filter and its Application

In this letter, a novel optical duobinary (ODB) downlink access scheme using low pass filter was proposed. The ODB downlink signal was generated by one continuous-wave (CW) laser, one pseudo-random binary sequence (PRBS) generator, one NRZ generator, one precoder, one Mach-Zehnder modulator and one low pass Bessel filter. The downlink signal can be transmitted over 20km singlemode fiber (SMF) and successfully received. We analyzed the time-domain waveforms, optical spectrum and eye diagrams before and after downstream transmission. The simulation results show that, compared to the traditional downlink scheme, this scheme has the advantages of high bandwidth efficiency, resistance to dispersion and good reception performance.

Chaos-based pseudo-random binary sequence generator

Chaos-based pseudo-random binary sequence generator

Scrambling and De-Scrambling Implementation Using Linear Feedback Shift Register Method on FPGA

communication system, a long sequence of bits ‘0’ or ‘1’ will inherits the loss of bit synchronization, and hence it can cause the false detection on the receiver. To avoid this, long sequence of bits will be randomized first so that long sequence of bits ‘0’ or ‘1’ can be removed. This randomization process is called scrambling and the circuit that works for the process is a scrambler. In the receiver there is a descrambler that serves to return the bits to their original information. This paper presents a design of scrambler and descrambler using a combination of Linear Feedback Shift Register (LFSR) with 15 registers, XOR logic gates, and Pseudo Random Binary Sequence (PRBS) generator structure with polynomial 1 + x14 + x15. One of the two main parts of LFSR is the shift register while the other is the feedback. In LFSR, the bits contained within the selected position in the shift register will be combined in a function and the result will be put back into this register's input bit. Feedback also makes the system more stable and no error occurrence. Then special tap is taken from a certain point in XOR and returned as a feedback register. The system is implemented on FPGA board Altera De0-Nano EP4CE22F17C6 Cyclone IV E. Resource memory required &lt;1% of available memory. Bit rate that can be achieved with clock speed 50MHz is 335570.47 bps.

A Power and Area Efficient Architecture of a PRBS Generator With Multiple Outputs

This brief presents a technique for achieving a power and area efficient high-speed pseudo-random binary sequence generator (PRBSG) with multiple decorrelated outputs. This architecture uses modules consisting of a novel half-rate PRBSG and a speed doubler block (SDB). The SDB can be cascaded to achieve any desired higher speed multioutput PRBSG in the module. A systematic procedure for designing such a module for a 27-1 PRBSG is discussed. The same technique can be extended for longer length sequences. The proposed architecture is implemented using field-programmable gate array. The quarter-rate implementation shows a 20% and 51% reduction in power and area (number of slices), respectively, when the proposed architecture is compared with the commonly used architecture. The proposed architecture is also synthesized for an integrated circuit implementation in a low-leakage 65-nm CMOS technology. Post-layout simulations show 30.5% and 50.6% reduction in power consumption and area, respectively, when the proposed architecture is compared with the commonly used architecture.

Embedded RSFQ Pseudorandom Binary Sequence Generator for Multichannel High-Speed Digital Data Link Testing and Synchronization

As the digital data links for superconducting circuits advance and higher data throughput per channel becomes possible, timing margins shrink and data integrity becomes a major challenge. Particular interest for multichannel applications is establishing the high-quality data link to interface with subsequent electronics. In this paper, we focus on integration of an on-chip pseudorandom binary sequence (PRBS) generator into a superconducting analog-to-digital converter (ADC) design to facilitate link stability evaluation and automated interchannel synchronization. PRBS generator and the ADC use a common clock source. An on-chip deserializer/demux, which includes the output drivers, is driven by a set of data sources depending on switch selections on-chip. The outputs are connected to a field-programmable gate array (FPGA) at room temperature, which hosts the developed interface circuitry for data reception, data integrity evaluation, and the synchronization mechanism. The integrated circuit (IC) that combines ADC and PRBS7 generator circuit was designed for the HYPRES 4.5 kA/cm2 four-layer standard fabrication process and features four deserialized outputs. A second similar IC was designed comprising an ADC frontend as well as a PRBS15 generator and was fabricated in the MIT-LL 10 kA/cm2 process. The implemented alignment engine that bonds the individual channels into a single data link was proven up to 10 Gbps while taking 1–2 μ s to complete the alignment. We built chip-to-FPGA data links, comprising the on-chip driver and room-temperature interface amplifier, up to 14 Gbps using FPGA serial-link GTY transceiver. Successful data transport from an ADC using multiple parallel data links to an FPGA upon completion of the channel bonding was demonstrated.

СНИЖЕНИЕ ВЫЧИСЛИТЕЛЬНОЙ СЛОЖНОСТИ МАШИННЫХ ЭКСПЕРИМЕНТОВ ПРИ ВЕРИФИКАЦИИ КРИПТОГРАФИЧЕСКИХ АЛГОРИТМОВ

The problem of obtaining a set of samples for the assessment of cryptographic algorithms quality on the basis of statistical tests use is considered. New properties of Markov binary chains taking into account dependences of probabilities of binary vectors with different length are described. The analytical expressions allowing the computation of dependences of range limits in values of probabilities of multidimen-sional binary random values upon probabilities of bi-nary random values with smaller dimension are of-fered. The reasons for the necessity of an additional procedure of rejection at the simulation of the realiza-tion of Markov binary processes are defined. A method for the directed search of probability values of sets in the distribution of Markov binary sequences allowing the generation of ergodic binary random sequences that allows refusing completely the procedure of rejection is considered. An algorithm realizing a mentioned method possessing a lowered computational complexity in comparison with the wellknown algorithms for the organization of a computational experiment on the investigation of statistical properties of binary random sequences is presented.

General simulation algorithm for autocorrelated binary processes.

The apparent ubiquity of binary random processes in physics and many other fields has attracted considerable attention from the modeling community. However, generation of binary sequences with prescribed autocorrelation is a challenging task owing to the discrete nature of the marginal distributions, which makes the application of classical spectral techniques problematic. We show that such methods can effectively be used if we focus on the parent continuous process of beta distributed transition probabilities rather than on the target binary process. This change of paradigm results in a simulation procedure effectively embedding a spectrum-based iterative amplitude-adjusted Fourier transform method devised for continuous processes. The proposed algorithm is fully general, requires minimal assumptions, and can easily simulate binary signals with power-law and exponentially decaying autocorrelation functions corresponding, for instance, to Hurst-Kolmogorov and Markov processes. An application to rainfall intermittency shows that the proposed algorithm can also simulate surrogate data preserving the empirical autocorrelation.

A Low-Phase Noise ADPLL Based on a PRBS-Dithered DDS Enhancement Circuit

This paper aims to design an all-digital phase-locked loop (ADPLL) intended for professional digital audio data conversion applications. The method used for designing is based on an analogy between analog PLL and ADPLL. Managing a low-jitter effect, a comparative study between discrete voltage-controlled oscillator (DVCO) and direct digital synthesis (DDS) based on a pseudorandom binary sequence (PRBS) generator is performed. The features of the design in this work are high-precision and low harmonic distortion DDS which is combined with ADPLL. For model-based design validation, a rapid register transfer level (RTL) with VHSIC hardware description language (VHDL) is practiced and the dynamic performance result indicates a significant improvement in total harmonic distortion (THD) ([Formula: see text][Formula: see text]dB) and a better resolution of 18.97[Formula: see text]bits for audio applications based on the aid of phase dithering DDS enhancement circuit.

Design and Implementation of Quadri phase Sequences with Good Merit Factor Values

Objective: Design of quadriphase codes with superior merit factor in basically a nonlinear multivariable optimization problem. Quadriphase transformation is applied to low side lobes in bi phase generation of binary sequence. In order to provide real time hardware for identification and generation of quadriphase pulse compression sequences. Methods/ Statistical Analysis: An efficient VLSI architecture has been proposed. The objectives to achieve high main lobe and low side lobes by poly phase codes. Findings: Initially pulse compression techniques are applied followed by binary quadriphase transformation. By applying a transformation to the biphase code using of sub pulses consequently results in the generation of codes. Near constant envelopes are created. Improvements/Applications: The systematic quadriphase sequences are useful for application to radar and continuation. There is scope for further development of merit factor. Keywords: Merit Factor (MF), Pseudo Random Binary Sequence (PRBS) Generator, Pulse Compression, Quadriphase Sequence

A 40-Gb/s 211-1 PRBS With Distributed Clocking and a Trigger Countdown Output

A 2 11 -1 pseudo-random binary sequence (PRBS) generator with trigger synchronization output (9.77-MHz rate) is implemented using synthetic transmission lines for the clock distribution. The full-rate data sequence is sourced from a 2:1 multiplex of dual shift register outputs synchronized to a half-rate clock. Quadrature half-rate clocks generated by a dual-mode (Dynastat) divide-by-2 are distributed via the synthetic lines to optimize power-speed tradeoffs in the design. The 790 × 620 μm 2 PRBS designed in 130-nm SiGe BiCMOS (200/280 GHz f T /fmax) consumes 250 mA at 2.5 V (i.e., 625 mW).