Embedded RSFQ Pseudorandom Binary Sequence Generator for Multichannel High-Speed Digital Data Link Testing and Synchronization

Abstract

As the digital data links for superconducting circuits advance and higher data throughput per channel becomes possible, timing margins shrink and data integrity becomes a major challenge. Particular interest for multichannel applications is establishing the high-quality data link to interface with subsequent electronics. In this paper, we focus on integration of an on-chip pseudorandom binary sequence (PRBS) generator into a superconducting analog-to-digital converter (ADC) design to facilitate link stability evaluation and automated interchannel synchronization. PRBS generator and the ADC use a common clock source. An on-chip deserializer/demux, which includes the output drivers, is driven by a set of data sources depending on switch selections on-chip. The outputs are connected to a field-programmable gate array (FPGA) at room temperature, which hosts the developed interface circuitry for data reception, data integrity evaluation, and the synchronization mechanism. The integrated circuit (IC) that combines ADC and PRBS7 generator circuit was designed for the HYPRES 4.5 kA/cm2 four-layer standard fabrication process and features four deserialized outputs. A second similar IC was designed comprising an ADC frontend as well as a PRBS15 generator and was fabricated in the MIT-LL 10 kA/cm2 process. The implemented alignment engine that bonds the individual channels into a single data link was proven up to 10 Gbps while taking 1–2 μ s to complete the alignment. We built chip-to-FPGA data links, comprising the on-chip driver and room-temperature interface amplifier, up to 14 Gbps using FPGA serial-link GTY transceiver. Successful data transport from an ADC using multiple parallel data links to an FPGA upon completion of the channel bonding was demonstrated.