Abstract
Multipliers are commonly used in ASICs and digital signal processors (DSPs). Field Programmable Gate Arrays (FPGAs) are now integrated with embedded modules, memory, DSPs, and logic blocks, requiring efficient Built-in self-tests (BISTs) for complex circuits such as DSP slices. The purpose of BIST is to validate the FPGA's functionality by introducing test patterns and examining the device's response. This paper evaluates the PRBS generator and checker used as a BIST for high data rate transfers in FPGAs. The design achieves less error with logic utilization of less than 2% in available LUT of FPGA. The testing of multipliers present in recent FPGAs is also discussed. Index terms include Built-in Self-test (BIST), Pseudo random binary sequence (PRBS) generator, checker, and BER-Bit Error Rate.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.