General-purpose Microprocessor Research Articles

Solar tracking system with fuzzy reasoning applied to crisp sets

In this paper, a low cost and an easy to implement solar tracker system is presented. The design of the system is based on the fuzzy reasoning applied to crisp sets. In this case, it can be easily implemented on general purpose microprocessor systems. Four light sensitive devices, such as LDR, photodiodes or phototransistors are mounted on the solar panel and placed in an enclosure. The four light detectors are screened from each other by opaque surfaces. Each pair of the light sensors is used to inform the controller on the orientation of the solar panel vertically and horizontally respectively.

ИССЛЕДОВАНИЕ ОГРАНИЧЕНИЙ ПРИМЕНИМОСТИ МИКРОПРОЦЕССОРОВ РЯДА ЭЛЬБРУС ДЛЯ РЕШЕНИЯ ЗАДАЧ ТЕХНИЧЕСКОГО ЗРЕНИЯ

One of the key areas in the artificial intelligence is technical vision. For resource-intensivetasks of technical vision high-performance, computing systems are created with use of specializedaccelerators. The use of such accelerators is necessary due to the inability of general-purposemicroprocessors (GPM) to solve such problems in a given time due to a high computational load.However, the microprocessors of Elbrus series are successfully used to solve technical visionproblems in both server and on-board modes, and the appearance of the sixth-generation Elbrusmicroprocessors should further improve performance on such tasks. Due to the high cost, greatercomplexity and limitations in the use of systems with specialized accelerators, the question arisesof determining the conditions under which, it is sufficient to use CPU’s to solve the tasks of technicalvision, for example, with the microprocessors of the Elbrus series without special accelerators.One of the most resource-intensive tasks in the field of technical vision are detection andclassification of objects. For the detection of objects one of the popular methods is the Viola-Jonesmethod. Convolutional neural networks are usually used to solve the classification problem.Mathematical models of computations have been developed for VGG16 and VGG19 neural networksin relation to the actual microprocessors of the Elbrus series. Using the developed models,the theoretical sufficiency of the performance of Elbrus microprocessors for technical vision tasksis substantiated. Also, based on these methods, programs for modeling detection and classificationsobjects in the image and video stream have been developed. The programs are written inC++ using the OpenCV library, OPO Elbrus, the GNS Platform library and the ImageNet competitiondatabase. Using the implemented programs, comparative testing was carried out on a numberof high-performance computing systems with Elbrus and Intel CPU’s and NVidia video card.Based on the results obtained, it is shown that the Elbrus-8S is sufficient to solve the problem ofsearching for objects in the image for input resolutions up to 1920 x 1080, where the processingspeed of the video stream is more than 20 frames per second.

Implementation of Booth Multiplier Algorithm using Radix-4 in FPGA

This paper presentsthe performance of Radix-4 Modified Booth Algorithm. Booth algorithm is a multiplication algorithm that multiplies two signed binary numbers in two's complement notation. Multiplier is a fundamental component in general-purpose microprocessors and in digital signal processors. With advances in technology, researchers design multipliers which offer high speed, low power, and less area implementation. Booth multiplier algorithm is designed to reduce number of partial products as compared to conventional multiplier. The proposed design is simulated by using Verilog HDL in Quartus II and implemented in Cyclone II FPGA. The result shows that the average output delay is 20.78 ns. The whole design has been verified by gate level simulation.

Reduction of Power in General Purpose Processor Through Clock-Gating Technique

Now a days DC power supply plays very important role in the Electronic industry because for every electronic gadget DC power is required to operate it. Even though durable DC batteries are available in the market to operate the various electronic gadgets for more time, electronic designers are continuously concentrating more and more to reduce the power through the various new Technologies like increasing parallel operations, pipe line concepts [1] etc. To work such durable batteries more duration than the actual duration what they can give, in this work we are concentrating on the 'clock-gating' technique to reduce the power in the general purpose microprocessor. For every microprocessor clock is required. All operations of any processor are performed by the clock cycle. There are various blocks in the processor but all the blocks are not operated at a time while using it, some blocks in the off mode while other blocks are in the working mode. Hence in order to power off such blocks for a little while clock gating is used in this work. Wherever particular block is not operated, for that block clock is disabled by the clock gating technique. The main principle of clock getting is nothing but ANDing the processor clock with a gate-control signal.

A Circuit-Level Amoeba-Inspired SAT Solver

AmbSAT (or AmoebaSAT) is a biologically-inspired stochastic local search (SLS) solver to explore solutions to the Boolean satisfiability problem (SAT). AmbSAT updates multiple variables in parallel at every iteration step, and thus AmbSAT can find solutions with a fewer number of iteration steps than some other conventional SLS solvers for a specific set of SAT instances. However, the parallelism of AmbSAT is not compatible with general-purpose microprocessors in that many clock cycles are required to execute each iteration; thus, AmbSAT requires special hardware that can exploit the parallelism of AmbSAT to quickly find solutions. In this paper, we propose a circuit model (hardware-friendly algorithm) that explores solutions to SAT in a similar way to AmbSAT, which we call circuit-level AmbSAT (CL-AmbSAT). We conducted numerical simulation to evaluate the search performance of CL-AmbSAT for a set of randomly generated SAT instances that was designed to estimate the scalability of our approach. Simulation results showed that CL-AmbSAT finds solutions with a fewer iteration number than a powerful SLS solver, ProbSAT, and outperforms even AmbSAT. Since CL-AmbSAT uses simple combinational logic to update variables, CL-AmbSAT can be easily implemented in various hardware.

Verification and Design Methods for the BrainScaleS Neuromorphic Hardware System

This paper presents verification and implementation methods that have been developed for the design of the BrainScaleS-2 65 nm ASICs. The 2nd generation BrainScaleS chips are mixed-signal devices with tight coupling between full-custom analog neuromorphic circuits and two general purpose microprocessors (PPU) with SIMD extension for on-chip learning and plasticity. Simulation methods for automated analysis and pre-tapeout calibration of the highly parameterizable analog neuron and synapse circuits and for hardware-software co-development of the digital logic and software stack are presented. Accelerated operation of neuromorphic circuits and highly-parallel digital data buses between the full-custom neuromorphic part and the PPU require custom methodologies to close the digital signal timing at the interfaces. Novel extensions to the standard digital physical implementation design flow are highlighted. We present early results from the first full-size BrainScaleS-2 ASIC containing 512 neurons and 130 K synapses, demonstrating the successful application of these methods. An application example illustrates the full functionality of the BrainScaleS-2 hybrid plasticity architecture.

Software Based Programmable IGBT IPM Dead-Time Insertion Module Using 16-bit Micro Controller for BLDC Motor Control Application with 3-Phase Sinusoidal and Trapezoidal Drive

Motor control application, especially for medium to high power implementation, will benefit the most with the compactness and robustness of an Integrated Power Module of Insulated Gate Bipolar Transistor also known as IGBT IPM. Nevertheless, implementation motor control with a general purpose micro-processor without any advance timer functionality with IGBT IPM will be challenged by the Dead-Time switching requirement in its power switching implementation. 
 
 Further, a combined sinusoidal and trapezoidal drive of a motor control is also believed will provides a better control performance in term of lower torque ripple and higher motor top speed. This paper proposed a low-cost alternative to address the requirement by implementing a software based dead time functionality using the low cost 16-bit micro controller board with capability of serving up sinusoidal drive as well as trapezoidal drive for motor control application.

Recommender system implementations for embedded collaborative filtering applications

This paper starts proposing a complete recommender system implemented on reconfigurable hardware with the purpose of testing on-chip, low-energy embedded collaborative filtering applications. Although the computing time is lower than the one obtained from usual multicore microprocessors, this proposal has the advantage of providing an approach to solve any prediction problem based on collaborative filtering by using an off-line, highly-portable light computing environment. This approach has been successfully tested with state-of-the-art datasets. Next, as a result of improving certain tasks related to the on-chip recommender system, we propose a custom, fine-grained parallel circuit for quick matrix multiplication with floating-point numbers. This circuit was designed to accelerate the predictions from the model obtained by the recommender system, and tested with two small datasets for experimental purposes. The accelerator is built from two levels of parallelism. On the one hand, several predictions run in parallel through the simultaneous multiplication of different vectors of two matrices. On the other hand, the operation of each vector is executed in parallel by multiplying pairs of floating-point values to later add the corresponding results in parallel as well. This circuit was compared with other approaches designed for the same purpose: circuits built using automatized tools of high-level synthesis, a general-purpose microprocessor, and high-performance graphical processing units. The performance of the prediction accelerator in terms of time surpassed that of the other approaches. We also evaluated the scalability of the circuit to practical problems using the high-level synthesis approach, and confirmed that implementations based on reconfigurable hardware allow acceptable speedups of multi-core processors.

An embedded machine vision system for an in-line quality check of assembly processes

In the context of the Industry 4.0 and Smart Manufacturing paradigm, this paper proposes a machine vision system for a flexible, precise and low-cost in-line geometric inspection of assembly processes. As a case study, the system has been targeted to the catalytic converter assembly process, in order to be easily integrated in the consolidated manufacturing flow. The system is based on developed algorithms to be applied on the image of the interfaces with the complete exhaust system the catalytic converter will be assembled into. An image segmentation procedure is described to robustly identify the region of interest (ROI) in the image. Afterwards, a geometrical model is proposed to detect any possible geometrical defects due to planar and/or rotational shifts of the interfaces around their expected positions. For the sake of validation, the proposed system has been implemented on a Raspberry Pi 3 Single Board Computer (SBC). It showed a sub-millimeter precision for planar movements and a maximum error in detecting the rotation angle lower than 1 degree, respectively. The modularity of the proposed approach makes it suitable to be realized also on different computational platforms, such as the modern heterogeneous System-on-Chips (SoC) hosting a general purpose microprocessor and a Field Programmable Gate Array (FPGA) on the same chip. Indeed, the most time-consuming computational steps can be efficiently realized on the FPGA, exploiting the parallel computing capability offered by a hardware implementation, thus accelerating the overall computation.

High performance parallel KMP algorithm on a heterogeneous architecture

String matching algorithm is widely used in many application areas such as bio-informatics, network intrusion detection, computer virus scan, among many others. KMP (Knuth-Morris-Pratt) algorithm is commonly used for its fast execution time compared with many other string matching algorithms when applied to large input texts. However, the performance of the KMP algorithm is limited when the input text size increases significantly beyond a certain limit. In this paper, we propose a high performance parallel KMP algorithm on the Heterogeneous High Performance Computing (HPC) architecture based on the general-purpose multicore microprocessor and the Graphic Processing Unit (GPU) using OpenCL as the GPGPU (General Purpose computing using Graphic Processing Unit) platform. The proposed parallel KMP algorithm mainly focuses on optimizing the CPU-GPU memory hierarchy by overlapping the data transfer between the CPU memory and the GPU memory with the string matching operations on the GPU. It also optimizes the allocation of the work-groups and the work-items, and places the pattern data and the Failure Table to the on-chip shared-memory of the GPU. The experimental results show that the optimized parallel KMP algorithm leads up to ~8 times faster execution time.

Delay Reduction in SDR Communication System

Data communication plays an important role nowadays, used in many applications like financial transactions, social interactions, education, national security and commerce. As there is increase in the growth in the mediums, people used to communicate i.e. data communications, voice communications video communications, etc. So, there is requirement for modification in the conventional radio devices. The Software defined radio is a technology in which software modules running on a generic hardware platform consisting of DSP's and general purpose microprocessors are used to implement radio functions. This paper presents two methods which increase the efficiency of SDR: The Standard beacon based SDR and parallel processing based SDR. The proposed system will reduce the delay of SDR using beacon based technique

Control System in Open-Source FPGA for a Self-Balancing Robot

Computing in technological applications is typically performed with software running on general-purpose microprocessors, such as the Computer Processing Unit (CPU), or specific ones, like the Graphical Processing Unit (GPU). Application-Specific Integrated Circuits (ASICs) are an interesting option when speed and reliability are required, but development costs are usually high. Field-Programmable Gate Arrays (FPGA) combine the flexibility of software with the high-speed operation of hardware, and can keep costs low. The dominant FPGA infrastructure is proprietary, but open tools have greatly improved and are a growing trend, from which robotics can benefit. This paper presents a robotics application that was fully developed using open FPGA tools. An inverted pendulum robot was designed, built, and programmed using open FPGA tools, such as IceStudio and the IceZum Alhambra board, which integrates the iCE40HX4K-TQ144 from Lattice. The perception from an inertial sensor is used in a PD control algorithm that commands two DC motors. All the modules were synthesized in an FPGA as a proof of concept. Its experimental validation shows good behavior and performance.

Towards Designing Asynchronous Microprocessors: From Specification to Tape-Out

Proceeding miniaturization in the VLSI circuits continues to pose challenges to the conventionally used synchronous design style in microprocessors. These include the distribution of clock in the GHz range, robustness to delay variations, reduction in electromagnetic interference, and energy conservation, to name a few. The asynchronous logic has been known for its ability to address the aforementioned challenges by means of the closed-loop handshake protocols, instead of notorious clock signals. Because of these advantages, there have been numerous attempts on building general and special purpose microprocessors during the last three decades. Still, however, the number of asynchronous processors commercially available is scarce, mainly due to an insufficient electronic design and automation tools support, an ambiguous design flow and testing mechanisms for asynchronous logic and, most importantly, absence of a forum to look for relevant works, explaining the design steps and tools for such microprocessors. This paper is intended to bridge this gap by 1) reviewing the design principles of asynchronous logic, including classification, signaling conventions, and pipelining approaches; 2) presenting the complete design flow and available electronic design and automation tools; 3) developing an encyclopedia of various general and special purpose microprocessors proposed by far; and 4) presenting an evaluation of those works in terms of area on the die and performance metrics. This paper will also serve as guidelines for the asynchronous microprocessor design and implementation in all phases from specification to tape-out.

Predicting New Workload or CPU Performance by Analyzing Public Datasets

The marketplace for general-purpose microprocessors offers hundreds of functionally similar models, differing by traits like frequency, core count, cache size, memory bandwidth, and power consumption. Their performance depends not only on microarchitecture, but also on the nature of the workloads being executed. Given a set of intended workloads, the consumer needs both performance and price information to make rational buying decisions. Many benchmark suites have been developed to measure processor performance, and their results for large collections of CPUs are often publicly available. However, repositories of benchmark results are not always helpful when consumers need performance data for new processors or new workloads . Moreover, the aggregate scores for benchmark suites designed to cover a broad spectrum of workload types can be misleading. To address these problems, we have developed a deep neural network (DNN) model, and we have used it to learn the relationship between the specifications of Intel CPUs and their performance on the SPEC CPU2006 and Geekbench 3 benchmark suites. We show that we can generate useful predictions for new processors and new workloads . We also cross-predict the two benchmark suites and compare their performance scores. The results quantify the self-similarity of these suites for the first time in the literature. This work should discourage consumers from basing purchasing decisions exclusively on Geekbench 3, and it should encourage academics to evaluate research using more diverse workloads than the SPEC CPU suites alone.

Low Power Robust Early Output Asynchronous Block Carry Lookahead Adder with Redundant Carry Logic

Adder is an important datapath unit of a general-purpose microprocessor or a digital signal processor. In the nanoelectronics era, the design of an adder that is modular and which can withstand variations in process, voltage and temperature are of interest. In this context, this article presents a new robust early output asynchronous block carry lookahead adder (BCLA) with redundant carry logic (BCLARC) that has a reduced power-cycle time product (PCTP) and is a low power design. The proposed asynchronous BCLARC is implemented using the delay-insensitive dual-rail code and adheres to the 4-phase return-to-zero (RTZ) and the 4-phase return-to-one (RTO) handshaking. Many existing asynchronous ripple-carry adders (RCAs), carry lookahead adders (CLAs) and carry select adders (CSLAs) were implemented alongside to perform a comparison based on a 32/28 nm complementary metal-oxide-semiconductor (CMOS) technology. The 32-bit addition was considered for an example. For implementation using the delay-insensitive dual-rail code and subject to the 4-phase RTZ handshaking (4-phase RTO handshaking), the proposed BCLARC which is robust and of early output type achieves: (i) 8% (5.7%) reduction in PCTP compared to the optimum RCA, (ii) 14.9% (15.5%) reduction in PCTP compared to the optimum BCLARC, and (iii) 26% (25.5%) reduction in PCTP compared to the optimum CSLA.

AnRAD: A Neuromorphic Anomaly Detection Framework for Massive Concurrent Data Streams.

The evolution of high performance computing technologies has enabled the large-scale implementation of neuromorphic models and pushed the research in computational intelligence into a new era. Among the machine learning applications, unsupervised detection of anomalous streams is especially challenging due to the requirements of detection accuracy and real-time performance. Designing a computing framework that harnesses the growing computing power of the multicore systems while maintaining high sensitivity and specificity to the anomalies is an urgent research topic. In this paper, we propose anomaly recognition and detection (AnRAD), a bioinspired detection framework that performs probabilistic inferences. We analyze the feature dependency and develop a self-structuring method that learns an efficient confabulation network using unlabeled data. This network is capable of fast incremental learning, which continuously refines the knowledge base using streaming data. Compared with several existing anomaly detection approaches, our method provides competitive detection quality. Furthermore, we exploit the massive parallel structure of the AnRAD framework. Our implementations of the detection algorithm on the graphic processing unit and the Xeon Phi coprocessor both obtain substantial speedups over the sequential implementation on general-purpose microprocessor. The framework provides real-time service to concurrent data streams within diversified knowledge contexts, and can be applied to large problems with multiple local patterns. Experimental results demonstrate high computing performance and memory efficiency. For vehicle behavior detection, the framework is able to monitor up to 16000 vehicles (data streams) and their interactions in real time with a single commodity coprocessor, and uses less than 0.2 ms for one testing subject. Finally, the detection network is ported to our spiking neural network simulator to show the potential of adapting to the emerging neuromorphic architectures.

PWM and PFM Hybrid Control Method for LLC Resonant Converters in High Switching Frequency Operation

High switching frequency is an effective method to improve power density for LLC resonant converters. However, conventional digital controllers, such as general-purpose digital signal processors and microprocessors, have limited frequency resolution, which induces high primary- and secondary-side current variation and leads to poor output voltage regulation. In this paper, a hybrid control method combining pulse frequency modulation (PFM) and pulse width modulation is proposed to overcome the limited frequency resolution issue. The proposed hybrid control method focuses on steady-state operation, and its operating principles are introduced and analyzed. In addition, the proper magnetizing inductance and dead time duration are derived to ensure that the power mosfet s achieve zero voltage switching with the proposed control method. The improved voltage regulation performance is compared with the conventional PFM control and verified through simulation and experimental results using a 240 W prototype converter operating at a switching frequency of 1 MHz.

A hybrid fixed-function and microprocessor solution for high-throughput broad-phase collision detection

We present a hybrid system spanning a fixed-function microarchitecture and a general-purpose microprocessor, designed to amplify the throughput and decrease the power dissipation of collision detection relative to what can be achieved using CPUs or GPUs alone. The primary component is one of the two novel microarchitectures designed to perform the principal elements of broad-phase collision detection. Both microarchitectures consist of pipelines comprising a plurality of memories, which rearrange the input into a format that maximises parallelism and bandwidth. The two microarchitectures are combined with the remainder of the system through an original method for sharing data between a ray tracer and the collision-detection microarchitectures to minimise data structure construction costs. We effectively demonstrate our system using several benchmarks of varying object counts. These benchmarks reveal that, for over one million objects, our design achieves an acceleration of 812 × relative to a CPU and an acceleration of 161 × relative to a GPU. We also achieve energy efficiencies that enable the mitigation of silicon power-density challenges, while making the design amenable to both mobile and wearable computing devices.

Analyzing Behavior Specialized Acceleration

Hardware specialization has become a promising paradigm for overcoming the inefficiencies of general purpose microprocessors. Of significant interest are Behavioral Specialized Accelerators (BSAs), which are designed to efficiently execute code with only certain properties, but remain largely configurable or programmable. The most important strength of BSAs -- their ability to target a wide variety of codes -- also makes their interactions and analysis complex, raising the following questions: can multiple BSAs be composed synergistically, what are their interactions with the general purpose core, and what combinations favor which workloads? From a methodological standpoint, BSAs are also challenging, as they each require ISA development, compiler and assembler extensions, and either simulator or RTL models. To study the potential of BSAs, we propose a novel modeling technique called the Transformable Dependence Graph (TDG) - a higher level alternative to the time-consuming traditional compiler+simulator approach, while still enabling detailed microarchitectural models for both general cores and accelerators. We then propose a multi-BSA organization, called ExoCore, which we model and study using the TDG. A design space exploration reveals that an ExoCore organization can push designs beyond the established energy-performance frontiers for general purpose cores. For example, a 2-wide OOO processor with three BSAs matches the performance of a conventional 6-wide OOO core, has 40% lower area, and is 2.6x more energy efficient.

Analyzing Behavior Specialized Acceleration

Hardware specialization has become a promising paradigm for overcoming the inefficiencies of general purpose microprocessors. Of significant interest are Behavioral Specialized Accelerators (BSAs), which are designed to efficiently execute code with only certain properties, but remain largely configurable or programmable. The most important strength of BSAs -- their ability to target a wide variety of codes -- also makes their interactions and analysis complex, raising the following questions: can multiple BSAs be composed synergistically, what are their interactions with the general purpose core, and what combinations favor which workloads? From a methodological standpoint, BSAs are also challenging, as they each require ISA development, compiler and assembler extensions, and either simulator or RTL models. To study the potential of BSAs, we propose a novel modeling technique called the Transformable Dependence Graph (TDG) - a higher level alternative to the time-consuming traditional compiler+simulator approach, while still enabling detailed microarchitectural models for both general cores and accelerators. We then propose a multi-BSA organization, called ExoCore, which we model and study using the TDG. A design space exploration reveals that an ExoCore organization can push designs beyond the established energy-performance frontiers for general purpose cores. For example, a 2-wide OOO processor with three BSAs matches the performance of a conventional 6-wide OOO core, has 40% lower area, and is 2.6x more energy efficient.