Abstract
This paper presents verification and implementation methods that have been developed for the design of the BrainScaleS-2 65 nm ASICs. The 2nd generation BrainScaleS chips are mixed-signal devices with tight coupling between full-custom analog neuromorphic circuits and two general purpose microprocessors (PPU) with SIMD extension for on-chip learning and plasticity. Simulation methods for automated analysis and pre-tapeout calibration of the highly parameterizable analog neuron and synapse circuits and for hardware-software co-development of the digital logic and software stack are presented. Accelerated operation of neuromorphic circuits and highly-parallel digital data buses between the full-custom neuromorphic part and the PPU require custom methodologies to close the digital signal timing at the interfaces. Novel extensions to the standard digital physical implementation design flow are highlighted. We present early results from the first full-size BrainScaleS-2 ASIC containing 512 neurons and 130 K synapses, demonstrating the successful application of these methods. An application example illustrates the full functionality of the BrainScaleS-2 hybrid plasticity architecture.
Highlights
The design of neuromorphic hardware follows the goal to model parts, or at least functional aspects, of the biological nervous system
For TrueNorth and Loihi these strategies have been outlined in [5] and [15], respectively. Such information is otherwise only sparsely available. To improve on this situation, this paper describes selected aspects of the implementation and verification strategies employed in the design of different versions of the BrainScaleS-2 neuromorphic chips
The mixed-signal BrainScaleS-2 ASIC contains very-large-scale integration (VLSI) analog neuromorphic circuits, digital control and communication infrastructure, and one or more general-purpose microprocessors mainly intended to be used as plasticity processing units (PPUs)
Summary
The design of neuromorphic hardware follows the goal to model parts, or at least functional aspects, of the biological nervous system. TrueNorth [33] is a neuromorphic chip that integrates 4096 neurosynaptic cores to simulate 1 M neurons and 256 M synaptic connections at biological realtime It is fully digital and the cores are operated asynchronously. While the aforementioned systems are implemented using digital logic, analog neuromorphic designs make use of dedicated analog circuits as computational elements, which is beneficial in terms of energy and cost efficiency and their continuous-time operation reproduces the collective dynamics of neural networks more faithfully. Such information is otherwise only sparsely available To improve on this situation, this paper describes selected aspects of the implementation and verification strategies employed in the design of different versions of the BrainScaleS-2 neuromorphic chips.
Sign-in/Register to view highlights & summary Sign-in/Register to access full text options 
Free) 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
