Low Power Robust Early Output Asynchronous Block Carry Lookahead Adder with Redundant Carry Logic

Padmanabhan Balasubramanian,Douglas Maskell,Nikos Mastorakis

doi:10.3390/electronics7100243

Padmanabhan Balasubramanian, Douglas Maskell + Show 1 more

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https://doi.org/10.3390/electronics7100243

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Abstract

Adder is an important datapath unit of a general-purpose microprocessor or a digital signal processor. In the nanoelectronics era, the design of an adder that is modular and which can withstand variations in process, voltage and temperature are of interest. In this context, this article presents a new robust early output asynchronous block carry lookahead adder (BCLA) with redundant carry logic (BCLARC) that has a reduced power-cycle time product (PCTP) and is a low power design. The proposed asynchronous BCLARC is implemented using the delay-insensitive dual-rail code and adheres to the 4-phase return-to-zero (RTZ) and the 4-phase return-to-one (RTO) handshaking. Many existing asynchronous ripple-carry adders (RCAs), carry lookahead adders (CLAs) and carry select adders (CSLAs) were implemented alongside to perform a comparison based on a 32/28 nm complementary metal-oxide-semiconductor (CMOS) technology. The 32-bit addition was considered for an example. For implementation using the delay-insensitive dual-rail code and subject to the 4-phase RTZ handshaking (4-phase RTO handshaking), the proposed BCLARC which is robust and of early output type achieves: (i) 8% (5.7%) reduction in PCTP compared to the optimum RCA, (ii) 14.9% (15.5%) reduction in PCTP compared to the optimum BCLARC, and (iii) 26% (25.5%) reduction in PCTP compared to the optimum CSLA.

Highlights

In the nanoelectronics era, design-for-manufacturability issues such as process variability due to process-induced defects, device variability due to random dopant and atomistic fluctuations, hot carrier effects, negative bias temperature instability, stress-induced variation, electrostatic discharge etc. and other metrology issues are more pronounced compared to the microelectronics era [1,2]
(15.5%) reduction in power-cycle time product (PCTP) compared to the optimum BCLARC, and (iii) 26% (25.5%) reduction in PCTP compared to the optimum carry select adders (CSLAs)
Adder architectures such as the CSLA and the carry lookahead adders (CLAs) pave the way for better reduction in the forward latency compared to the ripple-carry adders (RCAs) architecture, with the CLA architecture more effectively reducing the forward latency compared to the CSLA architecture

Summary

Introduction

Design-for-manufacturability issues such as process variability due to process-induced defects, device variability due to random dopant and atomistic fluctuations, hot carrier effects, negative bias temperature instability, stress-induced variation, electrostatic discharge etc. and other metrology issues are more pronounced compared to the microelectronics era [1,2]. The synchronous design method may involve more than a 100% overhead [3] in specifying the practical timing of a digital circuit or system This is to compensate for any or a combination of the clock network delay, the clock jitter, unexpected statistical timing variation(s) of the combinational logic, storage elements and control logic etc. An asynchronous design method that is modular and which can innately cope with arbitrary variations in processes or parameters is preferable [5,6,7] Such an asynchronous design method corresponds to the input-output timing model [8], which utilizes delay-insensitive codes for data encoding (i.e., representation) and processing and adheres to the 4-phase return-to-zero (RTZ) or return-to-one (RTO) handshake protocol for data communication.

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