Reduction of Power in General Purpose Processor Through Clock-Gating Technique

R Prakash Rao,Prasanna Murali, P,Sree Chandra S,Fairooz Shaik,P Bala Murali Krishna

doi:10.35940/ijrte.a5927.0510121

Abstract

Now a days DC power supply plays very important role in the Electronic industry because for every electronic gadget DC power is required to operate it. Even though durable DC batteries are available in the market to operate the various electronic gadgets for more time, electronic designers are continuously concentrating more and more to reduce the power through the various new Technologies like increasing parallel operations, pipe line concepts [1] etc. To work such durable batteries more duration than the actual duration what they can give, in this work we are concentrating on the 'clock-gating' technique to reduce the power in the general purpose microprocessor. For every microprocessor clock is required. All operations of any processor are performed by the clock cycle. There are various blocks in the processor but all the blocks are not operated at a time while using it, some blocks in the off mode while other blocks are in the working mode. Hence in order to power off such blocks for a little while clock gating is used in this work. Wherever particular block is not operated, for that block clock is disabled by the clock gating technique. The main principle of clock getting is nothing but ANDing the processor clock with a gate-control signal.

Highlights

INTRODUCTIONNo system is operated in the nature. Power is two types, AC power and DC power
Without the power, no system is operated in the nature.Power is two types, AC power and DC power
AC power is used for all the electrical applications whereas DC power is used for all electronic applications

Summary

INTRODUCTION

No system is operated in the nature. Power is two types, AC power and DC power. Static current will flow from VDD to VSS when pull down transistor is on When such static current multiplied by ON resistance of pull up and pull down transistors it gives rise to static power of that particular logic circuit. Apart from this type of static power dissipation, at the transistor level in the nano meter range there are some other leakage powers which cannot be avoided. When the load capacitance is being charged or discharged, depending on operation of the logic circuit this dynamic power is produced. During evaluate stage vice-versa, that is Cg is discharged When it fully discharged PMOS will ON and NMOS goes OFF load capacitance is discharged or retains value depending on input to the pulldown network. When dynamic logic cell is not used in a cycle, clock gate signal prevents both Cg and CL from switching in the cycle

Clock- Gating

DESIGN OF GENERAL PURPOSE PROCESSOR WITH CLOCK-GATING

Data Path

Control Unit

SIMULATION RESULTS

CONCLUSION