General-purpose Microprocessor Research Articles

Microprocessors and digital ICs for motion control

This paper reviews the developments in microprocessors and digital ICs with a special attention to applications to motion control. First, the use of microprocessors and digital ICs in the control of electric motor drives is considered. General-purpose microprocessors and microcontrollers are then presented with emphasis on features that are necessary for the implementation of real-time control systems. High-performance advanced processors such as digital signal processors (DSPs), reduced-instruction-set computing (RISC) processors, and parallel processors are studied. Development and debugging tools required for developing sophisticated microprocessor-based control systems are considered. The capabilities of application-specific integrated circuits (ASICs) in motion control and their design process are examined. Typical application examples illustrating research work in digital motion control using microprocessors and digital ICs are presented. The potentials of new devices are considered for application to high-performance drive systems. Trends for future development of the microprocessor technology for motion control applications are projected.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

On the fundamentals of digital signal processing micros

This tutorial addresses some fundamental issues of presently available digital signal processing (DSP) micros which have matured within the last decade. The architecture of these devices is a modified version of a general purpose microprocessor tailored to the need for high computation speeds to execute DSP algorithms. This architecture, for most presently available DSP devices, uses extensive pipelining, multiple independent memories, parallel functional units and several innovative techniques to improve overall performance. The applications of these devices are spreading rapidly over a wide range of areas and, using various configurations, meet both non-real-time and real-time requirements. The choice of a DSP micro for a specific application is at present a matter of concern. These are the issues discussed briefly in this paper.

Automated verification of behavioral equivalence for microprocessors

Presents a new method for verifying, in a fully automated way, that two synchronous sequential circuits have the same input/output behavior. The method applies to designs in which a distinction between data path and control can be made, and in particular to microprocessors. The verification is carried out at the register-transfer level. In contrast with previous methods, our procedure is not limited by the total number of latches in the circuit: it runs in time that is independent of the width of the data path. A price has to be paid for this: the procedure does not always terminate, and may produce false negatives. We argue, however, that these problems should not come up when verifying general purpose microprocessors. We have implemented the procedure in Prolog on an IBM RS/6000 workstation, and have tried it on the Tamarack-3 microprocessor previously verified by J.J. Joyce (1990) with the interactive theorem prover HOL at the University of Cambridge. We have verified the equivalence of several alternative implementations to the original one, in times ranging from 11 to 26 s, and we have detected the errors in several incorrect implementations, in times ranging from 1 to 26 s. >

Hardware-software cosynthesis for digital systems

As system design grows increasingly complex, the use of predesigned components, such as general-purpose microprocessors can simplify synthesized hardware. While the problems in designing systems that contain processors and application-specific integrated circuit chips are not new, computer-aided synthesis of such heterogeneous or mixed systems poses unique problems. The authors demonstrate the feasibility of synthesizing heterogeneous systems by using timing constraints to delegate tasks between hardware and software so that performance requirements can be met. System functionality is captured using the HardwareC hardware description language. The synthesis of an Ethernet-based network coprocessor is discussed as an example. >

Highly parallel collision detection processor for intelligent robots

A collision detection VLSI processor is proposed in order to achieve ultrahigh-performance processing with an ideal parallel processing scheme. A large number of coordinate transformations and memory accesses to the obstacle memory are fully utilized in the processing algorithm, so that direct collision detection can be executed with a VLSI-oriented regular data flow. The structure of each processing element (PE) is very simple because a PE mainly consists of a COordinate Rotational DIgital Computer (CORDIC) arithmetic unit for the coordinate transformation and memories for the storage of manipulator and obstacle information. When 100 PEs are used for parallel processing, the performance is about 10,000 times faster than that of conventional approaches using a single general-purpose microprocessor. >

Special Issue on Computer Architecture for Robotics

In the realization of intelligent robots, highly intelligent manipulation and movement techniques are required such as intelligent man-machine interfaces, intelligent information processing for path planning and problem solutions, practical robot vision, and high-speed sensor signal processing. Thus, very high-speed processing to cope with vast amounts of data as well as the development of various algorithms has become important subjects. To fulfill such requirements, the development of high-performance computer architecture using advanced microelectronics technology is required. For these purposes, the development of implementing computer systems’ for robots will be classified as follows: (a) Use of general-purpose computers As the performance of workstations and personal computers is increased year by year, software development is the major task without requiring hardware development except the interfaces with peripheral equipment. Since current high-level languages and software can be applied, the approach is excellent in case of system development, but the processing performance is limited. (b) Use of commercially available (V) LSI chips This is an approach to design a computer system by the combination of commercially available LSIs. Since the development of both hardware and software is involved in this system development, the development period tends to be longer than in (a). These chips include general-purpose microprocessors, memory chips, digital signal processors (DSPs) and multiply-adder LSIs. Though the kinds of available chips are limited to some degree, the approach can cope with a considerably high-performance specifications because a number of chips can be flexibly used. (c) Design, development and system configuration of VLSI chips This is an approach to develop new special-purpose VLSI chips using ASIC (Application Specific Integrated Circuit) technology, that is, semicustom or full-custom technology. If these attain practical use and are marketed, they will be widely used as high-performance VLSI chips of the level (b). Since a very high-performance specification must be satisfied, the study of very high performance VLSI computer architecture becomes very important. But this approach involving chip development requires a very long period in the design-development from the determination of processor specifications to the system configuration using the fabricated chips. For the above three approaches, the order from the viewpoint of ease of development will be (a), (b) and (c), while that from the viewpoint of performance will be (c), (b) and (a). Each approach is not exclusive but is complementary each other. For example, the development of new chips by (c) can also give new impact as the components of (a) and (b). Further, the common point of these approaches is that performance improvement by highly parallel architecture becomes important. This special edition introduces, from the above standpoint, the latest information on the present state and' future prospects of the computer techniques in Japan. We hope that this edition will contribute to the development of this field.

A hardware implementation of an autoregressive algorithm

With short length data records, high-resolution spectral estimates can be obtained by constructing a model of the signal and using the model coefficients to calculate the spectrum. The bottlenecks associated with implementing modelling algorithms in hardware were identified using a test bed based on a general-purpose microprocessor. A comparison is made of the architecture required and speed obtained when the Burg autoregressive modelling algorithm is implemented on high-speed multiprocessor systems. The systems compared were the microprogrammable AMD29500 byte slice digital signal processor chips and the NEC mu PD77230 single-chip digital signal processor. Applications in the area of magnetic resonance imaging are discussed. Prototype systems would allow a sixteenth-order autoregressive model to be performed on a 256*128 medical image in 1 to 3 seconds.

A multiple floating point coprocessor architecture

General purpose microprocessor based computers usually speed their arithmetic processing performance by using a floating point co-processor. Because adding more co-processors represents neither a technological nor a cost problem we investigated a system based on a MIPS R2000 [2] and 4 floating point units. In this paper we show a block diagram of such an implementation and how two important scientific operations can be accelerated using a single unmodified data bus. A large percentage of the engineering applications are solved with the help of linear algebra methods like BLAS3 [4] algorithms; It is precisely for these primitives that the proposed architecture brings significant performance gains. The first operation described will be a matrix multiplication algorithm, its timing diagram and some results. Next a polynomial evaluation technique will be examined. Finally we show how to use the same ideas with various other microprocessors.

Microprocessor implementation of non-recursive linear delta-modulation filters

An implementation of non-recursive linear delta-modulation filters based on a general-purpose microprocessor, is presented. The two main characteristics of this implementation are simplicity and low cost.

A mechanically verified language implementation

This paper briefly describes a programming language, its implementation on a microprocessor via a compiler and link-assembler, and the mechanically checked proof of the correctness of the implementation. The programming language, called Piton, is a high-level assembly language designed for verified applications and as the target language for high-level language compilers. It provides executeonly programs, recursive subroutine call and return, stack based parameter passing, local variables, global variables and arrays, a user-visible stack for intermediate results, and seven abstract data types including integers, data addresses, program addresses and subroutine names. Piton is formally specified by an interpreter written for it in the computational logic of Boyer and Moore. Piton has been implemented on the FM8502, a general purpose microprocessor whose gate-level design has been mechanically proved to implement its machine code interpreter. The FM8502 implementation of Piton is via a function in the Boyer-Moore logic which maps a Piton initial state into an FM8502 binary core image. The compiler and link-assembler are both defined as functions in the logic. The implementation requires approximately 36K bytes and 1400 lines of prettyprinted source code in the Pure Lisp-like syntax of the logic. The implementation has been mechanically proved correct. In particular, if a Piton state can be run to completion without error, then the final values of all the global data structures can be ascertained from an inspection of an FM8502 core image obtained by running the core image produced by the compiler and link-assembler. Thus, verified Piton programs running on FM8502 can be thought of as having been verified down to the gate level.

Optimized software implementations of the modular exponentiation on general purpose microprocessors

In the last few years asymmetric cryptographic algorithms have become more and more popular. They can be used for encipherment, digital signatures, authentication, key management and key distribution and for other security mechanisms. Almost all of these algorithms use the modular exponentiation of large numbers and the effective performance of the arithmetical routines is of great importance. Besides hardware solutions or solutions on special processors, such as signal processors or transputers, software implementations on general purpose microprocessors are also interesting if these are permitted or even required by the application. In this paper techniques for the software implementation of modular exponentiation are presented and analysed. It will be shown that the arithmetic routines chosen can only reach an optimal performance when the processor used and the key length are taken into consideration.

32-bit microprocessors based on the TRON specification

The paper provides an introduction to the chip architecture of the TRON specification for the 32-bit general-purpose microprocessor. Brief descriptions are given of two classes of instruction formats, high-level instructions, addressing modes, memory management, and EIT (exception, interrupt and trap) processing, particularly concerning the design philosophy. Its relations with operating systems designed in other TRON subprojects are discussed. The technologies involved in the realization of 32-bit microprocessors based on the TRON specification and example products are also described.

Cellular array processor CAP and applications

The general-purpose, highly parallel, cellular array processor (CAP) we developed features multiple-instruction stream, multiple-data stream (MIMD) processing and image display. Processor elements can number in several hundreds. The present system uses 256 processors. Each processor element consists of a general-purpose microprocessor, memory, and a special VLSI chip that performs parallel-processing-specific functions such as processor communication and synchronization. The VLSI has two 2M byte/s independent common bus interfaces for data broadcating and six 15M bit/s serial communication ports for local data communication. The chip also can process image data in real time for multiple processors. Use of the communication interfaces enables a variety of processor networks to be configured. One CAP application has been computer graphics, in which ray tracing is used to generate quality images.

The design of an asynchronous microprocessor

Abstract : Prejudices are as tenacious in science and engineering as in any other human activity. One of the most firmly held prejudices in digital VLSI design is that asynchronous circuits-a.k.a. self-timed or delay-insensitive circuits-are necessarily slow and wasteful in area and logic. Whereas asynchronous techniques would be appropriate for control, they would be inadequate for data paths because of the cost of dual-rail encoding of data, the cost of generating completion signals for write operations on registers, and the difficulty of designing self-timed buses. Because a general-purpose microprocessor contains a complex data path, a corollary of the previous opinion is that it is impossible to design an efficient asynchronous microprocessor. Since we have been developing a design method for asynchronous circuits that gives excellent results, and since the above objections to large-scale data path designs are genuine but untested, we decided to pick up the gauntlet and design a complete processor. The design of an asynchronous microprocessor poses new challenges and opens new avenues to the computer architect. Hence, the experiment unavoidably developed a dual purpose: We are refining an already well-tested design method and we are starting a new series of experiments in asynchronous architectures. (As far as we know, this is the first entirely asynchronous microprocessor ever built.) The results we are reporting have a different implication depending on whether they are related to the first or second goal of the experiment. Whereas we are convinced that our design methods have reached maturity, we are quite aware that asynchronous techniques may influence the computer architects in completely new ways that this first design is just starting to explore.

Design considerations for a general-purpose microprocessor

The authors examine the performance, cost, and schedule tradeoffs made for the NS 32532, a 32-bit general-purpose microprocessor. Among its features are a 30-MHz clock frequency, three on-chip caches, a four-stage pipeline, and dedicated mechanisms for multiprocessing support. The authors describe the design constraints set by the VLSI processing and packaging technologies. They address the issue of market requirements by examining the software and hardware considerations for the microprocessor's target applications. After describing the functional partitioning choices, including the means for supporting a memory hierarchy and floating-point operations, they present the NS32532's microarchitecture. They then examine the microprocessor's system interface, the memory reference transactions, and the instruction-flow and data-flow monitoring mechanisms. Finally, the authors present an overview of the methodology adopted to accomplish the design within a strict schedule while achieving full functionality and meeting cost and performance goals. >

A CNC machining system for education

Abstract A computer numerical control (CNC) machining system has been developed. The system includes a three-axis milling/drilling machine, a microprocessor, system software, and an automatically programmed tools (APT) processor. The objective of developing this machining system is to enable new features to be introduced, especially for the educational environment. A unique feature of the system is the use of a general purpose microprocessor as a controller. The CNC system is designed to include fundamental features with simple software format and a small scale construction. These make the system a versatile educational tool. An APT processor is developed, which can be used to link a geometric file devised by a commercial computer aided design software package to the CNC machine. The cost trade-offs of using the newly designed system and a comparison with commercial systems are also included.

Implementation of the V60/V70 and its FRM function

A description is given of the V60/V70, the first commercially based, general-purpose 32-bit microprocessor in Japan. Its functions include on-chip floating-point operations, a high-level-language-oriented architecture, software debugging support, and support functions to promote a high level of system reliability. Because high reliability is so important, the V60/V70 contains functional redundancy monitoring (FRM) support functions. The discussion covers the overall design considerations, architecture, implementation, hazard detection and control, and FRM functions. The V60/V70 uses a TRON real-time operating system specification. >

Automatic unit delay execution circuit for digital signal processing systems based on general-purpose microprocessors

A simple circuit is proposed for automatic unit delay execution during the implementation of digital filters on general purpose microprocessors. The hardware overhead of the circuit is negligible, independent of the filter order and of the number of microprocessors (in the case of multimicroprocessor systems). The software overhead is zero. >

Graphics Controllers: An Overview

Computer graphics is a topic of rapidly growing importance in the field of computer science. It has always been one of the most spectacular branches of computer technology. Since vision provides one of the richest method of communication, it is therefore of extreme importance to improve the quality of visual communication. Also for applications like three dimensional graphics, animation etc., a high performance graphics system is inevitable.Due to all these reasons, special purpose hardware is used along with general purpose microprocessors to design graphics workstations. With the advance in VLSI technology, this special purpose hardware has been designed using a variety of chips. Depending on the extent to which these chips can unload the host processor of graphics related activities, we have classified the chips into four generations. A survey of these generations is presented in this paper.

A 32-bit CMOS microprocessor with on-chip cache and TLB

A 32-b general-purpose microprocessor has been developed using 1-/spl mu/m CMOS technology. The chip, containing 372 K transistors, operates at a 80-ns machine cycle time with a 5-V power supply. For virtual and hierarchical memory system support, a 64-entry full-associative translation lookaside buffer (TLB) and a 2-kbyte instruction cache are implemented on the chip. The internal access times for the TLB and cache are 22 and 18 ns, respectively. The microarchitecture has been designed to reduce the pipeline to three stages, simplifying the control path and obtaining high-speed performance. The data path of this chip is also enhanced with hardware, such as a barrel shifter and multiplier/divider. The chip performance has been measured to be 5.1 million instructions per second (MIPS) and 50-ns-access main memory.