General-purpose Architecture Research Articles

Inferring population dynamics in macaque cortex

Objective. The proliferation of multi-unit cortical recordings over the last two decades, especially in macaques and during motor-control tasks, has generated interest in neural ‘population dynamics’: the time evolution of neural activity across a group of neurons working together. A good model of these dynamics should be able to infer the activity of unobserved neurons within the same population and of the observed neurons at future times. Accordingly, Pandarinath and colleagues have introduced a benchmark to evaluate models on these two (and related) criteria: four data sets, each consisting of firing rates from a population of neurons, recorded from macaque cortex during movement-related tasks. Approach. Since this is a discriminative-learning task, we hypothesize that general-purpose architectures based on recurrent neural networks (RNNs) trained with masking can outperform more ‘bespoke’ models. To capture long-distance dependencies without sacrificing the autoregressive bias of recurrent networks, we also propose a novel, hybrid architecture (‘TERN’) that augments the RNN with self-attention, as in transformer networks. Main results. Our RNNs outperform all published models on all four data sets in the benchmark. The hybrid architecture improves performance further still. Pure transformer models fail to achieve this level of performance, either in our work or that of other groups. Significance. We argue that the autoregressive bias imposed by RNNs is critical for achieving the highest levels of performance, and establish the state of the art on the neural latents benchmark. We conclude, however, by proposing that the benchmark be augmented with an alternative evaluation of latent dynamics that favors generative over discriminative models like the ones we propose in this report.

DSA: Deformable Segmentation Attention for Multi-Scale Fisheye Image Segmentation

With a larger field of view (FOV) than ordinary images, fisheye images are becoming mainstream in the field of autonomous driving. However, the severe distortion problem of fisheye images also limits its application. The performance of neural networks designed for narrow FOV images degrades drastically for fisheye images, and the use of large composite models can improve the performance, but it brings huge time overhead and hardware costs. Therefore, we decided to balance real time and accuracy by designing the deformable segmentation attention(DSA) module, a generalpurpose architecture based on a deformable attention mechanism and a spatial pyramid architecture. The deformable mechanism serves to accurately extract feature information from fisheye images, together with attention to learn the global context and the spatial pyramid structure to balance multiscale feature information, thus improving the perception of fisheye images by traditional networks without increasing the amount of excessive computation. Lightweight networks such as SegNeXt equipped with the DSA module enable effective and rapid multi-scale segmentation of fisheye images in complex scenes. Our architecture achieves outstanding results on the WoodScape dataset, while our ablation experiments demonstrate the effectiveness of various parts of the architecture.

A superconducting quantum processor architecture design method for improving performance and reducing frequency collisions

More physical qubits and qubit connections integrated on a superconducting quantum processor can improve the ability to execute quantum programs, but on the other hand, they might increase the probability of frequency collisions. Considering a performance and frequency collisions trade-off, it is a feasible method to optimize processor architecture aiming at running specific quantum programs. To this end, we propose a method for designing superconducting quantum processor architectures for the purpose of running specific quantum programs. Different from existing methods, our method is mainly based on graph theory to optimize processor architecture design. First, we convert the trade-off problem into the optimization of the distance between two points as well as the maximum degree in the processor architecture graph. Second, we consider the actual physical routing constraints and build a mathematical model for the optimization problem. Finally, we propose an automatic processor architecture design flow based on the mathematical model, which is implemented with an improved genetic algorithm. To show the effectiveness of our method, we selected sixteen quantum programs with different qubit numbers and different functions for comparison. Simulation results show that the architecture schemes of our method outperform IBM’s general-purpose square lattice architecture schemes. Compared to the general-purpose architecture schemes, the architecture schemes of our method have an average performance improvement of 15.61% and a minimum reduction of 21.33% in the probability of frequency collisions. Furthermore, in most of the selected quantum programs, our architecture schemes perform better than the eff-5-freq’s architecture schemes, with an average 6.58% improvement in performance and a minimum 6.45% reduction in the probability of frequency collisions. Therefore, our method can provide superconducting quantum processor architecture design with better performance and lower probability of frequency collisions for quantum programs.

PrecTime: A deep learning architecture for precise time series segmentation in industrial manufacturing operations

The fourth industrial revolution creates ubiquitous sensor data in production plants. To generate maximum value out of these data, reliable and precise time series-based machine learning methods like temporal neural networks are needed. This paper proposes a novel sequence-to-sequence deep learning architecture for time series segmentation called PrecTime which tries to combine the concepts and advantages of sliding window and dense labeling approaches. The general-purpose architecture is evaluated on a real-world industry dataset containing the End-of-Line testing sensor data of hydraulic pumps. We are able to show that PrecTime outperforms five implemented state-of-the-art baseline networks based on multiple metrics. The achieved segmentation accuracy of around 96% shows that PrecTime can achieve results close to human intelligence in operational state segmentation within a testing cycle.

Design of an Application-specific VLIW Vector Processor for ORB Feature Extraction

In computer-vision feature extraction algorithms, compressing the image into a sparse set of trackable keypoints, empowers navigation-critical systems such as Simultaneous Localization And Mapping (SLAM) in autonomous robots, and also other applications such as augmented reality and 3D reconstruction. Most of those applications are performed in battery-powered gadgets featuring in common a very stringent power-budget. Near-to-sensor computing of feature extraction algorithms allows for several design optimizations. First, the overall on-chip memory requirements can be lessened, and second, the internal data movement can be minimized. This work explores the usage of an Application Specific Instruction Set Processor (ASIP) dedicated to perform feature extraction in a real-time and energy-efficient manner. The ASIP features a Very Long Instruction Word (VLIW) architecture comprising one RV32I RISC-V and three vector slots. The on-chip memory sub-system implements parallel multi-bank memories with near-memory data shuffling to enable single-cycle multi-pattern vector access. Oriented FAST and Rotated BRIEF (ORB) are thoroughly explored to validate the proposed architecture, achieving a throughput of 140 Frames-Per-Second (FPS) for VGA images for one scale, while reducing the number of memory accesses by 2 orders of magnitude as compared to other embedded general-purpose architectures.

Customized FPGA Design and Analysis of Soft-Core Processor for DNN

Transistor scaling has continued to yield significant performance gains. The general-purpose architecture will not suffice in this dark silicon era with the big data boom and growing emphasis on performance. Artificial neural networks and deep learning are sophisticated computing activities that cannot be optimally executed (accuracy, performance, and energy) on today's general-purpose computer architecture. The demand for domain-specific computer architectures is increasing. This paper suggests and evaluates a highly reconfigurable domain-specific design for deep learning and artificial neural networks to overcome these problems. An FPGA-based soft-core processor for deep neural network (DNN) acceleration is suggested in this paper. Using a combination of unicast and multicast for collective operations, the proposed FPGA accelerates the performance of the deep learning network. The suggested design outperforms the current general-purpose processor by 6.6 times, according to a thorough examination and comparison. The existing architecture's level of accuracy is retained.

Hierarchical Model of Architecture of Supercomputer Systems for Comparison and Ranking

The task of comparing the capabilities of computing systems with each other and forming various ratings has many possible goals. Here, there is the identification of trends, the promotion of proven general-purpose architectures, and the demonstration of superiority in a certain class of tasks, etc. It is, of course, not enough to describe the achieved performance for all these purposes, various rankings and comparisons use different levels of abstraction and generalization up to that level, which would allow to associate the identified performance indicators with certain features of the system. In practice, descriptions of the architectural peculiarities of systems in ratings are rather scarce, and the authors of the work solve the problem of development a formal description of computer systems of a relatively high level, which, at the same time, would allow to increase the required level of detail, corresponding to the goals of applied research. Such a hierarchical system description model has been proposed and tested on well-known systems from the Top50 and Top500 lists.

Domain-Specific Quantum Architecture Optimization

With the steady progress in quantum computing over recent years, roadmaps for upscaling quantum processors have relied heavily on the targeted qubit architectures. So far, similarly to the early age of classical computing, these designs have been crafted by human experts. These general-purpose architectures, however, leave room for customization and optimization, especially when targeting popular near-term QC applications. In classical computing, customized architectures have demonstrated significant performance and energy efficiency gains over general-purpose counterparts. In this paper, we present a framework for optimizing quantum architectures, specifically through customizing qubit connectivity. It is the first work that (1) provides performance guarantees by integrating architecture optimization with an optimal compiler, (2) evaluates the impact of connectivity customization under a realistic crosstalk error model, and (3) benchmarks on realistic circuits of near-term interest, such as the quantum approximate optimization algorithm (QAOA) and quantum convolutional neural network (QCNN). We demonstrate up to 59% fidelity improvement in simulation by optimizing the heavy-hexagon architecture for QAOA maxcut circuits, and up to 14% improvement on the grid architecture. For the QCNN circuit, architecture optimization improves fidelity by 11% on the heavy-hexagon architecture and 605% on the grid architecture.

Deep Learning Methods for Speed Estimation of Bipedal Motion from Wearable IMU Sensors.

The estimation of the speed of human motion from wearable IMU sensors is required in applications such as pedestrian dead reckoning. In this paper, we test deep learning methods for the prediction of the motion speed from raw readings of a low-cost IMU sensor. Each subject was observed using three sensors at the shoe, shin, and thigh. We show that existing general-purpose architectures outperform classical feature-based approaches and propose a novel architecture tailored for this task. The proposed architecture is based on a semi-supervised variational auto-encoder structure with innovated decoder in the form of a dense layer with a sinusoidal activation function. The proposed architecture achieved the lowest average error on the test data. Analysis of sensor placement reveals that the best location for the sensor is the shoe. Significant accuracy gain was observed when all three sensors were available. All data acquired in this experiment and the code of the estimation methods are available for download.

Efficient Hardware Architectures for Accelerating Deep Neural Networks: Survey

In the modern-day era of technology, a paradigm shift has been witnessed in the areas involving applications of Artificial Intelligence (AI), Machine Learning (ML), and Deep Learning (DL). Specifically, Deep Neural Networks (DNNs) have emerged as a popular field of interest in most AI applications such as computer vision, image and video processing, robotics, etc. In the context of developed digital technologies and the availability of authentic data and data handling infrastructure, DNNs have been a credible choice for solving more complex real-life problems. The performance and accuracy of a DNN is a way better than human intelligence in certain situations. However, it is noteworthy that the DNN is computationally too cumbersome in terms of the resources and time to handle these computations. Furthermore, general-purpose architectures like CPUs have issues in handling such computationally intensive algorithms. Therefore, a lot of interest and efforts have been invested by the research fraternity in specialized hardware architectures such as Graphics Processing Unit (GPU), Field Programmable Gate Array (FPGA), Application Specific Integrated Circuit (ASIC), and Coarse Grained Reconfigurable Array (CGRA) in the context of effective implementation of computationally intensive algorithms. This paper brings forward the various research works on the development and deployment of DNNs using the aforementioned specialized hardware architectures and embedded AI accelerators. The review discusses the detailed description of the specialized hardware-based accelerators used in the training and/or inference of DNN. A comparative study based on factors like power, area, and throughput, is also made on the various accelerators discussed. Finally, future research and development directions, such as future trends in DNN implementation on specialized hardware accelerators, are discussed. This review article is intended to guide hardware architects to accelerate and improve the effectiveness of deep learning research.

Fast, Accurate Processor Evaluation Through Heterogeneous, Sample-Based Benchmarking

Performance evaluation is a key task in computing and communication systems. Benchmarking is one of the most common techniques for evaluation purposes, where the performance of a set of representative applications is used to infer system responsiveness in a general usage scenario. Unfortunately, most benchmarking suites are limited to a reduced number of applications, and in some cases, rigid execution configurations. This makes it hard to extrapolate performance metrics for a general-purpose architecture, supposed to have a multi-year lifecycle, running dissimilar applications concurrently. The main culprit of this situation is that current benchmark-derived metrics lack generality, statistical soundness and fail to represent general-purpose environments. Previous attempts to overcome these limitations through random app mixes significantly increase computational cost (workload population shoots up), making the evaluation process barely affordable. To circumvent this problem, in this article we present a more elaborate performance evaluation methodology named BenchCast. Our proposal provides more representative performance metrics, but with a drastic reduction of computational cost, limiting app execution to a small and representative fraction marked through code annotation. Thanks to this labeling and making use of synchronization techniques, we generate heterogeneous workloads where every app runs simultaneously inside its Region Of Interest, making a few execution seconds highly representative of full application execution.

A real-time FPGA-based cluster finding algorithm for LHCb silicon pixel detector

Starting from the next LHC run, the upgraded LHCb High Level Trigger will process events at the full LHC collision rate (averaging 30 MHz). This challenging goal, tackled using a large and heterogeneous computing farm, can be eased addressing lowest-level, more repetitive tasks at the earliest stages of the data acquisition chain. FPGA devices are very well-suited to perform with a high degree of parallelism and efficiency certain computations, that would be significantly demanding if performed on general-purpose architectures. A particularly time-demanding task is the cluster-finding process, due to the 2D pixel geometry of the new LHCb pixel detector. We describe here a custom highly parallel FPGA-based clustering algorithm and its firmware implementation. The algorithm implementation has shown excellent reconstruction quality during qualification tests, while requiring a modest amount of hardware resources. Therefore it can run in the LHCb FPGA readout cards in real time, during data taking at 30 MHz, representing a promising alternative solution to more common CPU-based algorithms.

Risk-5: Controlled Approximations for RISC-V

Approximate Computing offers enhanced energy efficiency by exploring quality relaxation on applications. Application-agnostic hardware-level techniques can provide high benefits under certain scenarios, but their integration on a general-purpose architecture presents novel control challenges. We present Risk-5, an extension of the RISC-V architecture that implements control mechanisms to orchestrate multiple coexisting approximation techniques within an architecture. In Risk-5, approximate hardware capabilities are exposed to software through identification registers, data structures, and drivers that describe the nature and configuration parameters for each approximate design. This allows the software stack to control what and how much is approximated in an application. Control options range from activating or deactivating a certain approximation (e.g., approximating ALU operations), to configuring allowable error levels (e.g., for a configurable FPU), and configuring operation parameters that may lead to probabilistic errors (e.g., setting the refresh rate for an approximate SDRAM). Approximations may be dynamically configured and combined at runtime, allowing for simplified design space exploration. Finally, supervisor- and machine-level control allows for the use of certain approximations without requiring changes to applications. In this article, we discuss the implementation of different classes of approximation techniques, detailing and evaluating how they interact with each other. Risk-5 and the selected approximations are demonstrated in the functional level in a RISC-V ISA simulator augmented with an approximate computing framework. Our experiments evaluate how six applications from different computing domains behave when subjected to a combination of approximation techniques. Our results show how Risk-5 can bridge the gap between software and hardware approximations, allowing designers to easily evaluate energy-quality tradeoffs.

An STT-MRAM based reconfigurable computing-in-memory architecture for general purpose computing

Recently, many researches have proposed computing-in-memory architectures trying to solve von Neumann bottleneck issue. Most of the proposed architectures can only perform some application-specific logic functions. However, the scheme that supports general purpose computing is more meaningful for the complete realization of in-memory computing. A reconfigurable computing-in-memory architecture for general purpose computing based on STT-MRAM (GCIM) is proposed in this paper. The proposed GCIM could significantly reduce the energy consumption of data transformation and effectively process both fix-point calculation and float-point calculation in parallel. In our design, the STT-MRAM array is divided into four subarrays in order to achieve the reconfigurability. With a specified array connector, the four subarrays can work independently at the same time or work together as a whole array. The proposed architecture is evaluated using Cadence Virtuoso. The simulation results show that the proposed architecture consumes less energy when performing fix-point or float-point operations.

Effective runtime scheduling for high-performance graph processing on heterogeneous dataflow architecture

Graph processing is widely used in modern society, such as social networks, bioinformatics, and information networks. It is observed that the dataflow architecture has been demonstrated to effectively resolve the challenges of low instruction-level parallelism and branch mispredictions in the existing general-purpose architecture for graph applications. In this paper, toward a customized heterogeneous dataflow architecture that integrates the hardware advantages of both dataflow architecture and traditional control architecture, we propose a novel runtime system that can adaptively offload each subgraph to an appropriate underlying architecture. We also present a hybrid execution model to drive optimal performance. Our implementation on a CPU-FPGA platform shows that our approach achieves 2.2x throughput improvement over a state-of-art CPU-FPGA graph processing accelerator and 2.4x throughput improvement over a state-of-art FPGA-based design.

A fast and efficient SIMD track reconstruction algorithm for the LHCb upgrade 1 VELO-PIX detector

The upgraded CERN LHCb detector, due to start data taking in 2021, will have to reconstruct 4 TB/s of raw detector data in real time using commodity processors. This is one of the biggest real-time data processing challenges in any scientific domain. We present an intrinsically parallel reconstruction algorithm for the vertex detector of the LHCb experiment designed to optimally exploit multi-core general purpose architectures. We evaluate the algorithm on two high-end architectures from two different vendors and discuss in detail the impact of different SIMD Instruction Set Architecture extensions on the performance. We further compare the algorithm to current state-of-the-art scalar pattern recognition algorithms. We show a factor 2 speedup while achieving similar or better levels of physics performance.

Accelerating Nested Conditionals on CGRA With Tag-Based Full Predication Method

CGRA (Coarse-grained Reconfigurable Architecture) has been widely considered as one of the most promising computing architectures to exploit spatial parallelism. Compared with the typical general-purpose architectures which are instruction-driven, most of the state-of-art CGRAs are designed following the data-driven strategy, leading to difficulties while dealing with control-flow (nested if-then-else structures, NITE). Tackling with this problem, existing techniques such as partial predication and full predication introduce extra conditional move and select operations, while state-based full predication (SFP) introduces sleep and awake operations to correctly implement the basic function of NITE. Meanwhile, performance degradation is also incurred by these redundant operations. In this paper, a novel tag-based full predication (TFP) strategy is proposed, trying to eliminate redundant operations and thus accelerate NITE on CGRAs. The extra tag field is added to each instruction word to implement distributed nullification and parallel tag register (TReg) overwriting. Hardware support for TFP is present, and experimental validation is based on RTL-level simulation with manual mapping. Results show that our method achieves over 30% performance gain on average compared with SFP at the expense of around 5% additional power consumption and ignorable area overhead.

HLA Run Time Infrastructure: A Comparative Study

Distributed computer simulation systems use a general-purpose architecture known as HLA (High Level Architecture). HLA aims to provide common architecture for all types of distributed modeling and simulations by providing interoperability and reusability among simulations. A middleware known as RTI (Run Time Infrastructure) provides distributed simulation services under HLA. RTI offers a communication framework which is necessary for federates to interact during simulation process. Many RTI implementations are available commercially and are open source to achieve reusability and interoperability by implementing HLA. However, functionality and performance of RTI is based on its structure. This review presents the performance analysis of multiple RTI implementations, so that the best suitable RTI can be selected for a given simulation scenario and provides the structural comparison of central and service distributed RTI. It also presents the performance analysis of multiple RTI implementations and provides the structural comparison of CeRTI (Central Run Time Infrastructure) and SDRTI (Service Distributed Run Time Infrastructure). Many simulations use HLA, and RTI as basic part of these simulations. This comparative study describes characteristics of different RTIs, their comparisons and implementations that will help the reader to select suitable RTI according to environment and requirements.

Inside Project Brainwave's Cloud-Scale, Real-Time AI Processor

Growing computational demands from deep neural networks (DNNs), coupled with diminishing returns from general-purpose architectures, have led to a proliferation of Neural Processing Units (NPUs). This paper describes the Project Brainwave NPU (BW-NPU), a parameterized microarchitecture specialized at synthesis time for convolutional and recurrent DNN workloads. The BW-NPU deployed on an Intel Stratix 10 280 FPGA achieves sustained performance of 35 teraflops at a batch size of 1 on a large recurrent neural network (RNN).

An integrated practice system for learning programming in Python: design and evaluation

Over the past decades, computer science educators have developed a multitude of interactive learning resources to support learning in various computer science domains, especially in introductory programming. While such smart content items are known to be beneficial, they are frequently offered through different login-based systems, each with its own student identification for giving credits and collecting log data. As a consequence, using more than one kind of smart learning content is rarely possible, due to overhead for both teachers and students caused by adopting and using several systems in the context of a single course. In this paper, we present a general purpose architecture for integrating multiple kinds of smart content into a single system. As a proof of this approach, we have developed the Python Grids practice system for learning Python, which integrates four kinds of smart content running on different servers across two continents. The system has been used over a whole semester in a large-scale introductory programming course to provide voluntary practice content for over 600 students. In turn, the ability to offer four kinds of content within a single system enabled us to examine the impact of using a variety of smart learning content on students’ studying behavior and learning outcomes. The results show that the majority of students who used the system were engaged with all four types of content, instead of only engaging with one or two types. Moreover, accessing multiple types of content correlated with higher course performance, as compared to using only one type of content. In addition, weekly practice with the system during the course also correlated with better overall course performance, rather than using it mainly for preparing for the course final examination. We also explored students’ motivational profiles and found that students using the system had higher levels of motivation than those who did not use the system. We discuss the implications of these findings.