Abstract
Starting from the next LHC run, the upgraded LHCb High Level Trigger will process events at the full LHC collision rate (averaging 30 MHz). This challenging goal, tackled using a large and heterogeneous computing farm, can be eased addressing lowest-level, more repetitive tasks at the earliest stages of the data acquisition chain. FPGA devices are very well-suited to perform with a high degree of parallelism and efficiency certain computations, that would be significantly demanding if performed on general-purpose architectures. A particularly time-demanding task is the cluster-finding process, due to the 2D pixel geometry of the new LHCb pixel detector. We describe here a custom highly parallel FPGA-based clustering algorithm and its firmware implementation. The algorithm implementation has shown excellent reconstruction quality during qualification tests, while requiring a modest amount of hardware resources. Therefore it can run in the LHCb FPGA readout cards in real time, during data taking at 30 MHz, representing a promising alternative solution to more common CPU-based algorithms.
Highlights
The LHCb detector [1, 2] is a single-arm forward spectrometer, designed for precision studies of b- and c-hadrons produced in pp collisions
We have developed, implemented and characterized a clustering algorithm that can run on back-end FPGA-based DAQ cards during the detector readout [4, 5]
The structure of the clustering algorithm is applicable to a general pixel detector, but it has specific features that were tailored for the LHCb Vertex Locator detector (VELO) [7]
Summary
The LHCb detector [1, 2] is a single-arm forward spectrometer, designed for precision studies of b- and c-hadrons produced in pp collisions. One of the main limitations of the current detector is the maximum readout rate (1.1 MHz) of most sub-detectors, constraining trigger efficiencies, in hadronic channels. To overcome these limitations the LHCb experiment is undergoing an extensive upgrade in view of the upcoming third run of the LHC [3]. The upgraded LHCb data acquisition framework will challenge the whole data handling system due to the large amount of data that has to be processed In this respect, a common effort is being made to address heavily repetitive tasks at early DAQ stages, leaving to CPUs only the more complex ones. The features of this algorithm are based on a design developed within the INFN-RETINA R&D project [6]
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