Risk-5: Controlled Approximations for RISC-V

Abstract

Approximate Computing offers enhanced energy efficiency by exploring quality relaxation on applications. Application-agnostic hardware-level techniques can provide high benefits under certain scenarios, but their integration on a general-purpose architecture presents novel control challenges. We present Risk-5, an extension of the RISC-V architecture that implements control mechanisms to orchestrate multiple coexisting approximation techniques within an architecture. In Risk-5, approximate hardware capabilities are exposed to software through identification registers, data structures, and drivers that describe the nature and configuration parameters for each approximate design. This allows the software stack to control what and how much is approximated in an application. Control options range from activating or deactivating a certain approximation (e.g., approximating ALU operations), to configuring allowable error levels (e.g., for a configurable FPU), and configuring operation parameters that may lead to probabilistic errors (e.g., setting the refresh rate for an approximate SDRAM). Approximations may be dynamically configured and combined at runtime, allowing for simplified design space exploration. Finally, supervisor- and machine-level control allows for the use of certain approximations without requiring changes to applications. In this article, we discuss the implementation of different classes of approximation techniques, detailing and evaluating how they interact with each other. Risk-5 and the selected approximations are demonstrated in the functional level in a RISC-V ISA simulator augmented with an approximate computing framework. Our experiments evaluate how six applications from different computing domains behave when subjected to a combination of approximation techniques. Our results show how Risk-5 can bridge the gap between software and hardware approximations, allowing designers to easily evaluate energy-quality tradeoffs.