General-purpose Architecture Research Articles

Variability in the execution of multimedia applications and implications for architecture

Multimedia applications are an increasingly important workload for general-purpose processors. This paper analyzes frame-level execution time variability for several multimedia applications on general-purpose architectures. There are two reasons for such an analysis. First, it has been conjectured that complex features of such architectures (e.g., out-of-order issue) result in unpredictable execution times, making them unsuitable for meeting real-time requirements of multimedia applications. Our analysis tests this conjecture. Second, such an analysis can be used to effectively employ recently proposed adaptive architectures. We find that while execution time varies from frame to frame for many multimedia applications, the variability is mostly caused by the application algorithm and the media input. Aggressive architectural features induce little additional variability (and unpredictability) in execution time, in contrast to conventional wisdom. The presence of frame-level execution time variability motivates frame-level architectural adaptation (e.g., to save energy). Additionally, our results show that execution time generally varies slowly, implying it is possible to dynamically predict the behavior of future frames on a variety of hardware configurations for effective adaptation.

A Multithreaded Message Passing Interface (MPI) Architecture: Performance and Program Issues

This paper discusses a multithreaded software architecture for message-passing interface (MPI) software specification. The architecture is thread-safe, allows for concurrent communication over several communications media (multifabric communication), efficiently utilizes available hardware concurrency over a wide range of target platforms, and allows for concurrent communication and computation within the limits imposed by the hardware. The architecture is developed in the framework of the MPICH software architecture, a well-known MPI implementation used worldwide. The proposed architecture adopts wide portability of the MPICH design and remedies some of its deficiencies such as inefficient multifabric communication and non-thread-safety. The paper also considers the issues concerning development of high-performance portable message-passing systems for general-purpose architectures. The contributions of the paper are improving architecture and addressing thread safety of modern reliable messaging software, as well as identifying and taking advantage of inherent concurrency in the message-passing software itself.

A differentiated services implementation for high-performance TCP flows

The IETF’s recent differentiated services (DS) architecture, which specifies a scalable mechanism for treating packets differently, offers new opportunities for building end-to-end quality of service (QoS) systems. However, it also introduces new challenges. In particular, it is not clear whether TCP’s flow and congestion control mechanisms work well with the mechanisms used for end-to-end QoS. For that reason it is essential to analyze whether the existing DS mechanisms can be used with standard TCP implementations or whether it is necessary to wait for upcoming features introduced in future modified versions of TCP. The general-purpose architecture for reservation and allocation (GARA) supports flow-specific QoS specification, immediate and advance reservation, and online monitoring and control of both individual resources and heterogeneous resource ensembles. Using GARA, we evaluated actual DS mechanisms provided by Cisco routers. We present the results of this evaluation and discuss their impact on the performance of popular TCP implementations.

A comparative study of formal verification techniques for software architecture specifications

With the rapid growth of network computing, the demand for largedscale and complex software systems has increased dramatically. However, the development of largedscale and complex software systems is much more difficult and error prone. This is due to the fact that techniques and tools for assuring the correctness and reliability of software systems lag far behind the increasing growth in size and complexity of software systems. The concept of software architecture has recently emerged as a new way to improve our ability to effectively construct and maintain largedscale complex software systems. The architecture based development of software systems focuses on the architectural elements and their overall interconnection structure. Several Architectural Definition Languages (ADLs) have been proposed for specifying domain specific or general purpose architectures. On the other hand, formal verification is rapidly becoming a promising and automated method to ensure the accuracy and correctness of software systems. In this paper, we survey several architecture description languages and formal verification methods. We present an environment to conduct experiments to study the performance of five different verification tools on software architecture specifications. Based on these experiments, we are able to compare the efficiency of these verification tools in verifying certain software property.

Cellular architecture for Euclidean distance transformation

The Euclidean distance transform (EDT) is an important tool in image analysis. Previous work on computation of EDT is limited to sequential algorithms and parallel algorithms on general purpose architectures. The authors develop a fast parallel algorithm that is amenable for VLSI implementation. The VLSI architecture is presented. Results of implementation of the VLSI design in a commercial package are also presented, and confirm the speed and suitability of the new method for real-time applications.

Fractionally addressed delay lines

While traditional implementations of variable-length digital delay lines are based on a circular buffer accessed by two pointers, we propose an implementation where a single fractional pointer is used both for read and write operations. On modern general-purpose architectures, the proposed method is nearly as efficient as the popularinterpolated circular buffer, and it behaves well for delay-length modulations commonly found in digital audio effects. The physical interpretation of the new implementation shows that it is suitable for simulating tension or density modulations in wave-propagating media.

Supporting the Evolution of Teams With Transactions: A Design Architecture for Organizational Memory Systems

In this article, we present a general-purpose architecture and design metaphor for supporting the evolution of teams. The architecture is based on the premise that the role of organizational memory involves active support for accessing the relations and content of past, present, and future information-based artifacts of collaborative work. The evolutionary work support role and structure of memory are outlined and contrasted with existing research. A set of design requirements for supporting memory are presented and the concept of a collaborative transaction is introduced. The collaborative transaction concept is the basis for the TeamBox architecture and prototype, which shows that it is possible to generically support the evolutionary needs of collaborative work. The article ends with a discussion of limitations and future research issues.

A Flexible Algorithm for Multiprocessor Ray Tracing

Ray tracing programs are widely used to generate photo-realistic images, but the high computation time may discourage their implementation on single-processor machines; moreover, cost reduction of multi-processor general purpose architectures makes parallel rendering an attractive field of research. We propose a new algorithm which addresses the main issues of a parallel implementation of ray tracing on a message-passing-based machine. We adopt efficient strategies for dynamic workload distribution among processors, task synchronization and communication delay reduction. The resulting implementation is highly flexible, since any number of processors can be employed without introducing synchronization problems. We show an implementation of our algorithm on an nCUBE 2 supercomputer which is a general purpose parallel architecture with distributed memory. A theoretical evaluation of our algorithm allows us to identify a decreasing function for rendering times; the considered examples confirm the theoretical expectations showing that the efficiency of our system may reach up to the 91% of the value achievable by dividing the sequential rendering time by the number of processors employed.

Attribute grammars as a robust technical basis for a human–computer interaction general purpose architecture

In this paper, we present a Natural Language Interface (NLI) that combines some of the advantages of using general purpose grammars with some of the features found in semantic grammars. This is achieved by an Attribute Grammar so as to create an intermediate representation which is interpreted in terms of domain-specific routines. NLI has been used as a component of a Human–Computer Interaction (HCI) system, working on different domains. After a discussion of the theory underlying the system, two examples of the use of NLI on practical domains are described: the first is in the field of three-dimensional scene generation, the second in the field of road map car planning. Some evaluation issues are also included in this paper.

Optimal static 2-dimensional screen subdivision for parallel rasterization architectures

Designers of computer graphics hardware have used increasing device counts available from IC manufacturers to increase parallelism using techniques such as putting a longer pipeline of data path elements on integrated circuits, or developing designs which use an array of processors. Pixel-Planes 1–5 and PixelFlow ‡ ‡ Pixel-Planes 1–5 and PixelFlow were developed at the University of North Carolina. are examples of architectures which use an array of pixel processors for rasterization. Early generations of Pixel-Planes attempted to make these arrays as large as the display providing one processor for each display pixel. Later generations improved performance by grouping processors into multiple smaller arrays, subdividing the screen into sections of a corresponding size and having the arrays independently process the screen subdivisions. This paper describes simulations which were performed to determine the optimum size subdivision for a graphics computer which uses Pixel-Planes type parallelism, i.e. static two dimensional screen subdivision parallel polygon rasterization. We then develop a mathematical approach to determining the optimal subdivision size and show that it agrees well with the experimental data. For special purpose architectures we show that the optimal size depends not only on the polygon size but also on the silicon area consumed by the rasterizer overhead. The mathematical approach can be directly applied to special purpose architectures, and we show how it can be modified for use in analyzing algorithms developed for general purpose architectures such as the Intel Touchstone or Paragon, or the Thinking Machines CM-5.

General-purpose vision chip architecture for real-time machine vision

To solve the I/O bottleneck problem in existing vision systems and to realize versatile processing adaptive to various and changing environments, we propose a new vision chip architecture for applications such as robot vision. The chip has general-purpose processing elements (PEs) with each PE being directly connected to a photo detector (PD) and can implement various visual processing algorithms. We developed and simulated some sample programs for the chip and proved that they can be processed within 1 ms/frame, a rate that is high enough for high-speed visual feedback for robot control. Aiming to complete the chip, we are now developing test chips based on the architecture. The latest design has 8 x 8 PEs and PDs in an area 3.3 mm x 3.0 mm using a 0.8 μm CMOS process.

Design and analysis of hardware for high-performance prolog

Most Prolog machines have been based on specialized architectures. Our goal is to start with a general-purpose architecture and determine a minimal set of extensions for high-performance Prolog execution. We have developed both the architecture and optimizing compiler simultaneously, drawing on results of previous implementations. We find that most Prolog-specific operations can be done satisfactorily in software; however, there is a crucial set of features that the architecture must support to achieve the best Prolog performance. In this paper, the costs and benefits of special architectural features and instructions are analyzed. In addition, we study the relationship between the strength of compiler optimization and the benefit of specialized hardware. We demonstrate that our base architecture can be extended to include explicit support for Prolog with modest increase in chip area (13%), and yet attain a significant performance benefit (60–70%). Experiments using optimized code that approximates the output of future optimizing compilers indicate that special hardware support can still provide a performance benefit of 30–35%. The microprocessor described here, the VLSI-BAM, has been fabricated and incorporated into a working test system.

A Scalable Approach to Teleoperation

Due to the fast pace of computer instrumentation and technology, we are quickly approaching an age where on-line use of expensive research facilities will become commonplace. The consequences of this trend will be multifaceted. It will allow scientist and researchers to perform experiments and access data with greater ease without the burden some overhead associated with working onsite. It will allow for the on-line storage and analysis of data. And lastly, an ideal testbed will be provided for integrating intelligent man-machine interfaces in order to reduce labor intensive tasks. This will simplify the control of complicated instruments via automation of the controls whose human control is not essential. Unfortunately, attempts at building a common platform for remote operation will face several problems. First of all, a successful general purpose architecture will frequently need to be extended in order to perform new functions as well as utilize new hardware. Similarly, the continued development of new microscopes, stage controls, etc. will undoubtedly create incompatible interfaces which will break presently working systems. Lastly, the environment that such a system will operate will likely be characterized by heterogeneous hardware and software. Based on the experience of building on-line systems for use of optical and electron microscopes, we propose a scalable system architecture based on the principles of object oriented design and analysis, a machine independent user- interface based on Java, and a software bus that supports distributed objects over the network.

ARCHON: framework for intelligent co-operation

The paper describes the work that has taken place in the ARCHON Project, ESPRIT project P-2256. The consortium has developed a general-purpose architecture, which can be used to facilitate co-operative problem-solving in industrial applications. The paper describes the need for a multiple agent approach for industrial applications, outlines the benefits which can be accrued by adopting this paradigm, and describes the key difficulties which must be faced when building a multi-agent system in this domain. Details of the ARCHON architecture are presented, including a description of the main functional components and their realisation in a hybrid agent model. An example of co-operative fault diagnosis in an electricity management application is described in order to provide a clear illustration of the working of the ARCHON architecture, and to provide a concrete example of the potential benefits of a multi-agent approach.

Processor reconfiguration through instruction-set metamorphosis

The processor reconfiguration through instruction-set metamorphosis (PRISM) general-purpose architecture, which speeds up computationally intensive tasks by augmenting the core processor's functionality with new operations, is described. The PRISM approach adapts the configuration and fundamental operations of a core processing system to the computationally intensive portions of a targeted application. PRISM-1, an initial prototype system, is described, and experimental results that demonstrate the benefits of the PRISM concept are presented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

MARVIN and TINA: A multiprocessor 3-D vision system

We describe a working multi-transputer stereo vision system which exploits various forms of parallelism in a number of visual competences upon a specialized hardware architecture that provides distributed video datapaths to the processor array. We exploit stereo and spatial parallelism to recover 3-D scene descriptions from passive stereo vision. To recognize and recover the positions of modelled objects, we exploit featural parallelism at both the object and sub-object level. We also describe a real-time object-tracking algorithm that exploits featural parallelism in the concurrent tracking of a set of object features. These competences have been integrated into a general-purpose architecture and we present some performance results and descriptions of the use of this vision engine in two application domains.

Petri net performance modeling of a modified mesh-connected parallel computer

A new message-passing computer architecture called the modified mesh-connected parallel computer (MMCPC) is proposed and studied. The MMCPC is designed to be a general-purpose parallel architecture suitable for wafer scale integration. Stochastic Petri nets (SPN) are used to model the behavior of the MMCPC. Both the one-dimensional and two-dimensional SPN models of the MMCPC are presented.

EMBEDDING LEARNING IN A GENERAL FRAME-BASED ARCHITECTURE

This research seeks to .incorporate machine learning capabilities within a general-purpose frame-based architecture. We describe CHUNKER, an explanation-based chunking mechanism built on top of THEO, a software framework to support development of self-modifying problem solving systems. CHUNKER forms rules that improve problem solving efficiency, by generalizing and compressing the chains of inference which THEO produces during problem solving. After presenting the learning algorithm used by CHUNKER, we illustrate its application to learning search control knowledge, discuss its relationship to THEO’s other three learning mechanisms, and consider the relationship between architectural features of THEO and the effectiveness of CHUNKER.

Fast Prolog with an extended general purpose architecture

Most Prolog machines have been based on specialized architectures. Our goal is to start with a general purpose architecture and determine a minimal set of extensions for high performance Prolog execution. We have developed both the architecture and optimizing compiler simultaneously, drawing on results of previous implementations. We find that most Prolog specific operations can be done satisfactorily in software; however, there is a crucial set of features that the architecture must support to achieve the best Prolog performance. The emphasis of this paper is on our architecture and instruction set. The costs and benefits of the special architectural features and instructions are analyzed. Simulated performance results are presented and indicate a peak compiled Prolog performance of 3.68 million logical inferences per second.

Inter: An inexpensive inter-procedural register allocator

Traditionally general-purpose architectures include few registers (8–16) which could easily be utilized by conventional (global) register allocation. Recently designed architectures require the compiler to utilize significantly more registers (⩾ 32). Exploitation of these larger sets by the compiler requires advanced register-allocation strategies. This paper describes inter, a register allocator which utilizes an interprocedural strategy to achieve excellent register-file utilizations.